| /art/runtime/interpreter/mterp/arm64/ |
| op_rem_int.S | 1 %include "arm64/binop.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"}
|
| op_rem_int_2addr.S | 1 %include "arm64/binop2addr.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"}
|
| op_rem_int_lit16.S | 1 %include "arm64/binopLit16.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"}
|
| op_rem_int_lit8.S | 1 %include "arm64/binopLit8.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"}
|
| op_rem_long.S | 1 %include "arm64/binopWide.S" {"preinstr":"sdiv x3, x1, x2","instr":"msub x0, x3, x2, x1", "chkzero":"1"}
|
| op_rem_long_2addr.S | 1 %include "arm64/binopWide2addr.S" {"preinstr":"sdiv x3, x0, x1", "instr":"msub x0, x3, x1, x0", "chkzero":"1"}
|
| /external/capstone/suite/MC/Mips/ |
| micromips-multiply-instructions-EB.s.cs | 4 0x00,0xa4,0xeb,0x3c = msub $4, $5
|
| micromips-multiply-instructions.s.cs | 4 0xa4,0x00,0x3c,0xeb = msub $4, $5
|
| /sdk/eclipse/plugins/com.android.ide.eclipse.ndk/src/com/android/ide/eclipse/ndk/internal/templates/ |
| TemplatedInputStream.java | 30 private char[] mSub;
49 if (mSub != null) {
50 char c = mSub[mPos++];
51 if (mPos >= mSub.length)
52 mSub = null;
67 mSub = str.toCharArray();
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fast-isel-rem.ll | 16 ; CHECK: msub w0, [[TMP]], w1, w0
24 ; CHECK: msub x0, [[TMP]], x1, x0
32 ; CHECK: msub w0, [[TMP]], w1, w0
40 ; CHECK: msub x0, [[TMP]], x1, x0
|
| arm64-neon-mul-div.ll | 333 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
341 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
343 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
345 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
347 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
349 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
351 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
353 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
355 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
363 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}
[all...] |
| madd-combiner.ll | 17 ; CHECK-NEXT: msub {{w[0-9]+}}, w0, w1, [[REG]]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| mips4010.s | 12 msub $8,$9
|
| mips4-fp.s | 24 msub.d $f0,$f2,$f4,$f6
25 msub.s $f0,$f2,$f4,$f6
|
| mips32.s | 16 msub $9, $10
|
| mips4010.d | 16 0+001c <stuff\+0x1c> msub t0,t1
|
| mips4-fp.d | 31 [0-9a-f]+ <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
32 [0-9a-f]+ <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
|
| /external/valgrind/none/tests/mips64/ |
| fpu_arithmetic.stdout.exp | [all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/d30v/ |
| mul.s | 2 # IU: MUL, MAC, MACS, MSUB, MSUBS (a)
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32r2.s | 10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/webrtc/webrtc/common_audio/signal_processing/ |
| filter_ar_fast_q12_mips.c | 54 "msub %[r0], %[r1] \n\t"
55 "msub %[r2], %[r3] \n\t"
94 "msub %[r0], %[r1] \n\t"
95 "msub %[r2], %[r3] \n\t"
101 "msub %[r0], %[r1] \n\t"
|
| /external/llvm/test/MC/Mips/ |
| micromips-multiply-instructions.s | 14 # CHECK-EL: msub $4, $5 # encoding: [0xa4,0x00,0x3c,0xeb]
21 # CHECK-EB: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
25 msub $4, $5
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| madd-msub.ll | 35 ; CHECK: msub
57 ; CHECK: msub
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| itrans32_cols_dspr2.c | 65 "msub $ac1, %[load2], %[cospi_1_64] \n\t"
78 "msub $ac2, %[load4], %[cospi_17_64] \n\t"
94 "msub $ac1, %[load2], %[cospi_4_64] \n\t"
125 "msub $ac1, %[load2], %[cospi_9_64] \n\t"
138 "msub $ac2, %[load4], %[cospi_25_64] \n\t"
153 "msub $ac1, %[load1], %[cospi_28_64] \n\t"
154 "msub $ac1, %[load2], %[cospi_4_64] \n\t"
155 "msub $ac3, %[load1], %[cospi_4_64] \n\t"
185 "msub $ac1, %[load2], %[cospi_5_64] \n\t"
198 "msub $ac2, %[load4], %[cospi_21_64] \n\t
[all...] |
| itrans32_dspr2.c | 109 "msub $ac1, %[load2], %[cospi_1_64] \n\t"
122 "msub $ac2, %[load4], %[cospi_17_64] \n\t"
138 "msub $ac1, %[load2], %[cospi_4_64] \n\t"
169 "msub $ac1, %[load2], %[cospi_9_64] \n\t"
182 "msub $ac2, %[load4], %[cospi_25_64] \n\t"
197 "msub $ac1, %[load1], %[cospi_28_64] \n\t"
198 "msub $ac1, %[load2], %[cospi_4_64] \n\t"
199 "msub $ac3, %[load1], %[cospi_4_64] \n\t"
229 "msub $ac1, %[load2], %[cospi_5_64] \n\t"
242 "msub $ac2, %[load4], %[cospi_21_64] \n\t
[all...] |
