| /art/runtime/interpreter/mterp/arm/ |
| op_or_long.S | 1 %include "arm/binopWide.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"}
|
| op_or_long_2addr.S | 1 %include "arm/binopWide2addr.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"}
|
| op_or_int.S | 1 %include "arm/binop.S" {"instr":"orr r0, r0, r1"}
|
| op_or_int_2addr.S | 1 %include "arm/binop2addr.S" {"instr":"orr r0, r0, r1"}
|
| op_or_int_lit16.S | 1 %include "arm/binopLit16.S" {"instr":"orr r0, r0, r1"}
|
| op_or_int_lit8.S | 1 %include "arm/binopLit8.S" {"extract":"", "instr":"orr r0, r0, r3, asr #8"}
|
| /art/runtime/interpreter/mterp/arm64/ |
| op_or_int.S | 1 %include "arm64/binop.S" {"instr":"orr w0, w0, w1"}
|
| op_or_int_2addr.S | 1 %include "arm64/binop2addr.S" {"instr":"orr w0, w0, w1"}
|
| op_or_int_lit16.S | 1 %include "arm64/binopLit16.S" {"instr":"orr w0, w0, w1"}
|
| op_or_int_lit8.S | 1 %include "arm64/binopLit8.S" {"extract":"", "instr":"orr w0, w0, w3, asr #8"}
|
| op_or_long.S | 1 %include "arm64/binopWide.S" {"instr":"orr x0, x1, x2"}
|
| op_or_long_2addr.S | 1 %include "arm64/binopWide2addr.S" {"instr":"orr x0, x0, x1"}
|
| op_const_wide.S | 9 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
10 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
11 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| pr19721.s | 5 orr x7, xzr, x17, lsl 25
|
| rm-simd-ext.l | 2 [^:]*:27: Error: selected processor does not support `orr v0.16b,v1.16b,v2.16b'
|
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-operand-rm-orr-a32.h | 38 0x0e, 0x40, 0x85, 0xd1 // orr le r4 r5 r14
41 0x0a, 0x50, 0x8b, 0xa1 // orr ge r5 r11 r10
44 0x09, 0x00, 0x89, 0x91 // orr ls r0 r9 r9
47 0x02, 0x80, 0x87, 0xd1 // orr le r8 r7 r2
50 0x0d, 0x10, 0x8a, 0x01 // orr eq r1 r10 r13
53 0x02, 0x90, 0x8c, 0xd1 // orr le r9 r12 r2
56 0x05, 0x60, 0x81, 0x51 // orr pl r6 r1 r5
59 0x06, 0x10, 0x8c, 0xa1 // orr ge r1 r12 r6
62 0x03, 0xd0, 0x8c, 0x31 // orr cc r13 r12 r3
65 0x09, 0x20, 0x84, 0xc1 // orr gt r2 r4 r
[all...] |
| assembler-cond-rd-rn-operand-rm-orr-t32.h | 38 0x49, 0xea, 0x0b, 0x0c // orr al r12 r9 r11
41 0x44, 0xea, 0x0a, 0x03 // orr al r3 r4 r10
44 0x40, 0xea, 0x0c, 0x02 // orr al r2 r0 r12
47 0x49, 0xea, 0x0d, 0x09 // orr al r9 r9 r13
50 0x42, 0xea, 0x04, 0x0b // orr al r11 r2 r4
53 0x43, 0xea, 0x07, 0x07 // orr al r7 r3 r7
56 0x46, 0xea, 0x09, 0x0b // orr al r11 r6 r9
59 0x47, 0xea, 0x0b, 0x08 // orr al r8 r7 r11
62 0x4c, 0xea, 0x0e, 0x0e // orr al r14 r12 r14
65 0x45, 0xea, 0x08, 0x08 // orr al r8 r5 r
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-rs-orr-a32.h | 38 0x18, 0x80, 0x8a, 0x41 // orr mi r8 r10 r8 LSL r0
41 0x7d, 0xb8, 0x84, 0x31 // orr cc r11 r4 r13 ROR r8
44 0x73, 0xd4, 0x8b, 0xe1 // orr al r13 r11 r3 ROR r4
47 0x34, 0xbb, 0x85, 0xc1 // orr gt r11 r5 r4 LSR r11
50 0x78, 0xcd, 0x80, 0x61 // orr vs r12 r0 r8 ROR r13
53 0x15, 0xa5, 0x8c, 0x51 // orr pl r10 r12 r5 LSL r5
56 0x12, 0xa9, 0x82, 0x91 // orr ls r10 r2 r2 LSL r9
59 0x39, 0xc7, 0x87, 0x01 // orr eq r12 r7 r9 LSR r7
62 0x70, 0x3b, 0x8d, 0x41 // orr mi r3 r13 r0 ROR r11
65 0x59, 0x9c, 0x80, 0xb1 // orr lt r9 r0 r9 ASR r1
[all...] |
| assembler-cond-rd-rn-operand-const-orr-a32.h | 38 0xff, 0x97, 0x84, 0xd3 // orr le r9 r4 0x03fc0000
41 0xff, 0xeb, 0x83, 0x53 // orr pl r14 r3 0x0003fc00
44 0xff, 0x15, 0x86, 0x33 // orr cc r1 r6 0x3fc00000
47 0xab, 0x57, 0x81, 0x33 // orr cc r5 r1 0x02ac0000
50 0xab, 0xe2, 0x84, 0x53 // orr pl r14 r4 0xb000000a
53 0xff, 0x2b, 0x8d, 0x23 // orr cs r2 r13 0x0003fc00
56 0xab, 0xd5, 0x80, 0x43 // orr mi r13 r0 0x2ac00000
59 0xff, 0x0a, 0x80, 0x73 // orr vc r0 r0 0x000ff000
62 0xff, 0x2e, 0x89, 0x63 // orr vs r2 r9 0x00000ff0
65 0xff, 0xf0, 0x87, 0x33 // orr cc r15 r7 0x000000f
[all...] |
| assembler-cond-rd-rn-operand-const-orr-t32.h | 38 0x4e, 0xf0, 0x2b, 0x7d // orr al r13 r14 0x02ac0000
41 0x41, 0xf4, 0xab, 0x1a // orr al r10 r1 0x00156000
44 0x40, 0xf4, 0x7f, 0x7a // orr al r10 r0 0x000003fc
47 0x4b, 0xf0, 0x2b, 0x51 // orr al r1 r11 0x2ac00000
50 0x46, 0xf4, 0xab, 0x18 // orr al r8 r6 0x00156000
53 0x4c, 0xf4, 0x7f, 0x07 // orr al r7 r12 0x00ff0000
56 0x43, 0xf4, 0x7f, 0x0c // orr al r12 r3 0x00ff0000
59 0x47, 0xf4, 0x7f, 0x44 // orr al r4 r7 0x0000ff00
62 0x4d, 0xf0, 0x2b, 0x6b // orr al r11 r13 0x0ab00000
65 0x4c, 0xf0, 0xff, 0x26 // orr al r6 r12 0xff00ff0
[all...] |
| assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-orr-t32.h | 38 0xc8, 0xbf, 0x03, 0x43 // It gt; orr gt r3 r3 r0
41 0xa8, 0xbf, 0x0e, 0x43 // It ge; orr ge r6 r6 r1
44 0xc8, 0xbf, 0x0f, 0x43 // It gt; orr gt r7 r7 r1
47 0xc8, 0xbf, 0x02, 0x43 // It gt; orr gt r2 r2 r0
50 0x08, 0xbf, 0x15, 0x43 // It eq; orr eq r5 r5 r2
53 0xc8, 0xbf, 0x00, 0x43 // It gt; orr gt r0 r0 r0
56 0xb8, 0xbf, 0x20, 0x43 // It lt; orr lt r0 r0 r4
59 0x88, 0xbf, 0x1e, 0x43 // It hi; orr hi r6 r6 r3
62 0xa8, 0xbf, 0x37, 0x43 // It ge; orr ge r7 r7 r6
65 0x08, 0xbf, 0x2d, 0x43 // It eq; orr eq r5 r5 r
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-orr-a32.h | 38 0x80, 0xd2, 0x8d, 0x01 // orr eq r13 r13 r0 LSL 5
41 0x0d, 0xa5, 0x8e, 0x41 // orr mi r10 r14 r13 LSL 10
44 0x0d, 0x62, 0x82, 0x81 // orr hi r6 r2 r13 LSL 4
47 0x0d, 0x31, 0x85, 0xa1 // orr ge r3 r5 r13 LSL 2
50 0x61, 0xa5, 0x85, 0x31 // orr cc r10 r5 r1 ROR 10
53 0xe7, 0x33, 0x8e, 0xa1 // orr ge r3 r14 r7 ROR 7
56 0x87, 0xbb, 0x81, 0x51 // orr pl r11 r1 r7 LSL 23
59 0x84, 0x8a, 0x86, 0xd1 // orr le r8 r6 r4 LSL 21
62 0x82, 0x21, 0x89, 0x11 // orr ne r2 r9 r2 LSL 3
65 0x08, 0xe2, 0x8e, 0xa1 // orr ge r14 r14 r8 LSL
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-orr-t32.h | 38 0x44, 0xea, 0xc7, 0x1c // orr al r12 r4 r7 LSL 7
41 0x48, 0xea, 0x7a, 0x57 // orr al r7 r8 r10 ROR 21
44 0x45, 0xea, 0x33, 0x35 // orr al r5 r5 r3 ROR 12
47 0x4d, 0xea, 0x8a, 0x5e // orr al r14 r13 r10 LSL 22
50 0x4a, 0xea, 0xbb, 0x09 // orr al r9 r10 r11 ROR 2
53 0x4b, 0xea, 0xc5, 0x3e // orr al r14 r11 r5 LSL 15
56 0x42, 0xea, 0x07, 0x72 // orr al r2 r2 r7 LSL 28
59 0x4b, 0xea, 0x71, 0x22 // orr al r2 r11 r1 ROR 9
62 0x42, 0xea, 0x08, 0x1b // orr al r11 r2 r8 LSL 4
65 0x4d, 0xea, 0x73, 0x06 // orr al r6 r13 r3 ROR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orr-a32.h | 38 0xc7, 0xd2, 0x86, 0x01 // orr eq r13 r6 r7 ASR 5
41 0x48, 0x80, 0x8b, 0x41 // orr mi r8 r11 r8 ASR 32
44 0x4a, 0x29, 0x83, 0x81 // orr hi r2 r3 r10 ASR 18
47 0x2e, 0xd0, 0x88, 0x91 // orr ls r13 r8 r14 LSR 32
50 0xc2, 0x81, 0x89, 0x31 // orr cc r8 r9 r2 ASR 3
53 0x25, 0xe1, 0x82, 0x91 // orr ls r14 r2 r5 LSR 2
56 0xc1, 0x8f, 0x86, 0x51 // orr pl r8 r6 r1 ASR 31
59 0xae, 0x21, 0x80, 0xd1 // orr le r2 r0 r14 LSR 3
62 0xad, 0x27, 0x80, 0x11 // orr ne r2 r0 r13 LSR 15
65 0x23, 0x94, 0x8c, 0xa1 // orr ge r9 r12 r3 LSR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orr-t32.h | 38 0x4d, 0xea, 0x6a, 0x2b // orr al r11 r13 r10 ASR 9
41 0x45, 0xea, 0xa2, 0x07 // orr al r7 r5 r2 ASR 2
44 0x42, 0xea, 0x5b, 0x15 // orr al r5 r2 r11 LSR 5
47 0x46, 0xea, 0x1a, 0x0e // orr al r14 r6 r10 LSR 32
50 0x46, 0xea, 0x53, 0x39 // orr al r9 r6 r3 LSR 13
53 0x44, 0xea, 0xd6, 0x7e // orr al r14 r4 r6 LSR 31
56 0x41, 0xea, 0x97, 0x32 // orr al r2 r1 r7 LSR 14
59 0x49, 0xea, 0x1c, 0x62 // orr al r2 r9 r12 LSR 24
62 0x4c, 0xea, 0xa4, 0x0a // orr al r10 r12 r4 ASR 2
65 0x4a, 0xea, 0x10, 0x26 // orr al r6 r10 r0 LSR
[all...] |
