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  /external/llvm/test/CodeGen/NVPTX/
addrspacecast.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -disable-nvptx-favor-non-generic | FileCheck %s -check-prefix=PTX64
9 ; PTX64: conv1
10 ; PTX64: cvta.global.u64
11 ; PTX64: ld.u32
21 ; PTX64: conv2
22 ; PTX64: cvta.shared.u64
23 ; PTX64: ld.u32
33 ; PTX64: conv3
34 ; PTX64: cvta.const.u64
35 ; PTX64: ld.u3
    [all...]
ld-generic.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
9 ; PTX64: ld.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
10 ; PTX64: ret
19 ; PTX64: ld.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
20 ; PTX64: ret
29 ; PTX64: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
30 ; PTX64: ret
39 ; PTX64: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
40 ; PTX64: ret
49 ; PTX64: ld.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}
    [all...]
st-generic.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
10 ; PTX64: st.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
11 ; PTX64: ret
21 ; PTX64: st.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
22 ; PTX64: ret
32 ; PTX64: st.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
33 ; PTX64: ret
43 ; PTX64: st.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
44 ; PTX64: ret
54 ; PTX64: st.f32 [%rd{{[0-9]+}}], %f{{[0-9]+}
    [all...]
ld-addrspace.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
9 ; PTX64: ld.global.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
10 ; PTX64: ret
18 ; PTX64: ld.shared.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
19 ; PTX64: ret
27 ; PTX64: ld.local.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
28 ; PTX64: ret
37 ; PTX64: ld.global.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
38 ; PTX64: ret
46 ; PTX64: ld.shared.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}
    [all...]
st-addrspace.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
10 ; PTX64: st.global.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
11 ; PTX64: ret
19 ; PTX64: st.shared.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
20 ; PTX64: ret
28 ; PTX64: st.local.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
29 ; PTX64: ret
39 ; PTX64: st.global.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
40 ; PTX64: ret
48 ; PTX64: st.shared.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}
    [all...]
global-addrspace.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
7 ; PTX64: .visible .global .align 4 .u32 i;
8 ; PTX64: .visible .const .align 4 .u32 j;
9 ; PTX64: .visible .shared .align 4 .u32 k;
local-stack-frame.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
10 ; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
11 ; PTX64: cvta.local.u64 %SP, %SPL;
12 ; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
13 ; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
25 ; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
26 ; PTX64: cvta.local.u64 %SP, %SPL;
27 ; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0];
28 ; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0;
29 ; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}}
    [all...]
global-ordering.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
9 ; PTX64: .visible .global .align 1 .u8 a = 2;
10 ; PTX64-NEXT: .visible .global .align 8 .u64 a2 = a;
17 ; PTX64: .visible .global .align 1 .u8 b = 1;
18 ; PTX64-NEXT: .visible .global .align 8 .u64 b2[2] = {b, b};
pr13291-i1-store.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
7 ; PTX64: mov.u16 %rs{{[0-9]+}}, 0;
8 ; PTX64-NEXT: st.global.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}};
18 ; PTX64: ld.global.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
19 ; PTX64: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
20 ; PTX64: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
symbol-naming.ll 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
8 ; PTX64-NOT: .str
13 ; PTX64-DAG: _$_str.1
14 ; PTX64-DAG: _$_str
  /external/swiftshader/third_party/LLVM/lib/Target/PTX/TargetInfo/
PTXTargetInfo.cpp 23 RegisterTarget<Triple::ptx64> X64(ThePTX64Target, "ptx64",
  /external/swiftshader/third_party/LLVM/test/CodeGen/PTX/
options.ll 9 ; RUN: llc < %s -march=ptx64 -mattr=ptx23 | grep ".address_size 64"
  /external/swiftshader/third_party/LLVM/lib/Target/PTX/MCTargetDesc/
PTXMCAsmInfo.cpp 21 if (TheTriple.getArch() == Triple::ptx64)
  /external/swiftshader/third_party/LLVM/lib/Support/
Triple.cpp 42 case ptx64: return "ptx64";
78 case ptx64: return "ptx";
182 if (Name == "ptx64")
183 return ptx64;
229 if (Str == "ptx64")
230 return Triple::ptx64;
266 if (Str == "ptx64")
267 return "ptx64";
327 else if (ArchName == "ptx64")
    [all...]
  /external/swiftshader/third_party/LLVM/include/llvm/ADT/
Triple.h 67 ptx64, // PTX: ptx (64-bit) enumerator in enum:llvm::Triple::ArchType

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