| /external/llvm/test/CodeGen/AMDGPU/ |
| codegen-prepare-addrmode-sext.ll | 9 ; SI-LLC: s_mul_i32
|
| mul.ll | 46 ; SI: s_mul_i32
74 ; SI-DAG: s_mul_i32
110 ; FUNC-LABEL: {{^}}s_mul_i32:
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
117 define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
159 ; SI: s_mul_i32
180 ; SI-DAG: s_mul_i32
|
| s_mulk_i32.ll | 35 ; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}}
|
| 32-bit-local-address-space.ll | 71 ; SI: s_mul_i32
|
| /external/llvm/test/MC/AMDGPU/ |
| sop2.s | 139 s_mul_i32 s2, s4, s6 label
140 // SICI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93]
141 // VI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
|
| trap.s | 89 s_mul_i32 ttmp8, 0x00000324, ttmp8 label
90 // SICI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
91 // VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| sop2_vi.txt | 75 # VI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
|
| trap_vi.txt | 67 # VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 274 MI.getOpcode() == AMDGPU::S_MUL_I32) {
|
| SIInstrInfo.cpp | 775 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
[all...] |
| SIInstructions.td | 301 defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
[all...] |
