| /device/linaro/bootloader/edk2/BeagleBoardPkg/Debugger_scripts/ |
| rvi_boot_from_ram.inc | 16 setreg @CP15_CONTROL = 0x0005107E
17 setreg @pc=0x80008208
18 setreg @cpsr=0x000000D3
|
| rvi_hw_setup.inc | 17 setreg @CP15_CONTROL = 0x0005107E
18 setreg @cpsr=0x000000D3
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
360 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
372 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
503 MO.setReg(High);
515 MO.setReg(High);
528 MO.setReg(High);
561 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
|
| HexagonPeephole.cpp | 252 MI.getOperand(0).setReg(PeepholeSrc);
282 MI.getOperand(PR).setReg(POrig);
305 Dst.setReg(Src.getReg());
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 125 SrcMO.setReg(NewVReg);
147 SrcMO.setReg(NewVReg);
|
| PPCVSXFMAMutate.cpp | 245 MI->getOperand(0).setReg(KilledProdReg);
246 MI->getOperand(1).setReg(KilledProdReg);
247 MI->getOperand(3).setReg(AddendSrcReg);
264 MI->getOperand(2).setReg(AddendSrcReg);
269 MI->getOperand(2).setReg(OtherProdReg);
|
| PPCMIPeephole.cpp | 156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCInst.h | 63 /// setReg - Set the register number.
64 void setReg(unsigned Reg) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| FPMover.cpp | 115 MI->getOperand(0).setReg(EvenDestReg);
116 MI->getOperand(1).setReg(EvenSrcReg);
|
| /device/linaro/bootloader/edk2/AppPkg/Applications/Lua/src/ |
| ldebug.c | 342 int setreg = -1; /* keep last instruction that changed 'reg' */ local
352 setreg = filterpc(pc, jmptarget);
357 setreg = filterpc(pc, jmptarget);
363 setreg = filterpc(pc, jmptarget);
378 setreg = filterpc(pc, jmptarget);
383 setreg = filterpc(pc, jmptarget);
387 return setreg;
|
| /external/syslinux/com32/lua/src/ |
| ldebug.c | 342 int setreg = -1; /* keep last instruction that changed 'reg' */ local
352 setreg = filterpc(pc, jmptarget);
357 setreg = filterpc(pc, jmptarget);
363 setreg = filterpc(pc, jmptarget);
378 setreg = filterpc(pc, jmptarget);
383 setreg = filterpc(pc, jmptarget);
387 return setreg;
|
| /external/capstone/ |
| MCInst.c | 114 /// setReg - Set the register number.
|
| MCInst.h | 62 /// setReg - Set the register number.
|
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 61 MI.getOperand(0).setReg(NewReg);
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 399 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
438 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
472 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
473 RestoreMI->getOperand(1).setReg(SP::G0);
|
| SparcRegisterInfo.cpp | 190 MI.getOperand(2).setReg(SrcOddReg);
203 MI.getOperand(0).setReg(DestOddReg);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyReplacePhysRegs.cpp | 90 MO.setReg(VReg);
|
| WebAssemblyPeephole.cpp | 65 MO.setReg(NewReg);
94 MO.setReg(NewReg);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AntiDepBreaker.h | 65 MI->getOperand(0).setReg(NewReg);
|
| DeadMachineInstructionElim.cpp | 144 nextI = llvm::next(I); // I is invalidated by the setReg
150 UseMI->getOperand(0).setReg(0U);
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 88 DstOp.setReg(AMDGPU::OQAP);
94 Mov->getOperand(MovPredSelIdx).setReg(
|
| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 138 I->getOperand(0).setReg(DstReg);
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZShortenInst.cpp | 96 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
101 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 69 void setReg(unsigned Reg) {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 134 MO.setReg(NewReg);
|
