| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| shift-and.ll | 5 %shamt = and i32 %t, 31
6 %res = shl i32 %val, %shamt
13 %shamt = and i16 %t, 31
15 %tmp1 = ashr i16 %tmp, %shamt
21 %shamt = and i64 %t, 63
22 %res = lshr i64 %val, %shamt
|
| vshift-5.ll | 12 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
13 %shl = shl <4 x i32> %val, %shamt
26 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
27 %shr = ashr <4 x i32> %val, %shamt
39 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
40 %shl = shl <4 x i32> %val, %shamt
52 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
53 %shr = ashr <4 x i32> %val, %shamt
|
| vshift-4.ll | 10 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
11 %shl = shl <2 x i64> %val, %shamt
21 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
22 %shl = shl <2 x i64> %val, %shamt
31 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
32 %shl = shl <4 x i32> %val, %shamt
41 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
42 %shl = shl <4 x i32> %val, %shamt
51 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
52 %shl = shl <4 x i32> %val, %shamt
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| 2004-11-30-shr-var-crash.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=1]
5 %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| 2004-11-30-shr-var-crash.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=1]
5 %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| shift-bmi2.ll | 4 define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
6 %shl = shl i32 %x, %shamt
28 define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
31 %shl = shl i32 %x, %shamt
54 define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
56 %shl = shl i64 %x, %shamt
72 define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
75 %shl = shl i64 %x, %shamt
92 define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
94 %shl = lshr i32 %x, %shamt
[all...] |
| shift-and.ll | 12 %shamt = and i32 %t, 31
13 %res = shl i32 %val, %shamt
25 %shamt = and i32 %t, 63
26 %res = shl i32 %val, %shamt
40 %shamt = and i16 %t, 31
42 %tmp1 = ashr i16 %tmp, %shamt
51 %shamt = and i64 %t, 63
52 %res = lshr i64 %val, %shamt
60 %shamt = and i64 %t, 191
61 %res = lshr i64 %val, %shamt
[all...] |
| vshift-5.ll | 12 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
13 %shl = shl <4 x i32> %val, %shamt
26 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
27 %shr = ashr <4 x i32> %val, %shamt
39 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
40 %shl = shl <4 x i32> %val, %shamt
52 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
53 %shr = ashr <4 x i32> %val, %shamt
|
| vshift-4.ll | 10 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
11 %shl = shl <2 x i64> %val, %shamt
26 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
27 %shl = shl <2 x i64> %val, %shamt
36 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
37 %shl = shl <4 x i32> %val, %shamt
46 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
47 %shl = shl <4 x i32> %val, %shamt
56 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
57 %shl = shl <4 x i32> %val, %shamt
[all...] |
| /external/llvm/test/ExecutionEngine/MCJIT/ |
| test-shift.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/ExecutionEngine/OrcMCJIT/ |
| test-shift.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/swiftshader/third_party/LLVM/test/ExecutionEngine/ |
| test-shift.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/ExecutionEngine/ |
| test-interp-vec-shift.ll | 4 %shamt = add <2 x i8> <i8 0, i8 0>, <i8 1, i8 2>
5 %shift.upgrd.1 = zext <2 x i8> %shamt to <2 x i32>
8 %shift.upgrd.2 = zext <2 x i8> %shamt to <2 x i32>
13 %shift.upgrd.5 = zext <2 x i8> %shamt to <2 x i32>
16 %shift.upgrd.6 = zext <2 x i8> %shamt to <2 x i32>
20 %shift.upgrd.7 = zext <2 x i8> %shamt to <2 x i64>
23 %shift.upgrd.8 = zext <2 x i8> %shamt to <2 x i64>
26 %shift.upgrd.9 = zext <2 x i8> %shamt to <2 x i64>
29 %shift.upgrd.10 = zext <2 x i8> %shamt to <2 x i64>
|
| /toolchain/binutils/binutils-2.27/cpu/ |
| iq2000.cpu | 149 (dnf f-shamt "shift amount field" () 10 5)
372 (dnop shamt "shift amount" () h-uint f-shamt)
458 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD)
464 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD)
495 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU)
501 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU)
507 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16)
516 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16)
525 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND
[all...] |
| iq2000m.cpu | 212 (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
242 (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
248 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
254 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
260 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
266 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
272 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
278 (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
284 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
290 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6)
[all...] |
| iq10.cpu | 287 (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD)
295 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32)
301 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B)
307 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S)
317 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL)
323 (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE)
329 (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD)
335 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR)
341 (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID)
347 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| mips64_disassem.c | 187 reg_name[i.RType.rt], i.RType.shamt);
190 if (i.RType.func == OP_SRLV && (i.RType.shamt & 1) == 1) {
197 if (i.RType.shamt == OP_MUL) {
199 } else if (i.RType.shamt == OP_MUH) {
207 if (i.RType.shamt == OP_MUL) {
209 } else if (i.RType.shamt == OP_MUH) {
238 i.RType.shamt);
292 i.RType.shamt,
298 i.RType.shamt,
304 i.RType.shamt,
[all...] |
| mips_opcode.h | 65 unsigned shamt: 5; member in struct:__anon2838::__anon2841
100 unsigned shamt: 5; member in struct:__anon2838::__anon2845
351 * Values for the 'shamt' field when OP_SPECIAL3 && func OP_BSHFL.
360 * Values for the 'shamt' field when OP_SOP30.
|
| mips_disassem.c | 222 reg_name[i.RType.rt], i.RType.shamt);
225 if (i.RType.func == OP_SRLV && (i.RType.shamt & 1) == 1) {
247 i.RType.shamt);
327 i.RType.shamt,
333 i.RType.shamt,
334 i.RType.rd-i.RType.shamt+1);
335 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_WSBH)
339 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEB)
343 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEH)
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
45 AddInstr(SeqLs, Inst(SLL, Shamt));
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| Mips64InstrInfo.td | 42 FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt, shamt_64:$shamt),
43 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
44 [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, (i64 PF:$shamt)))],
54 let shamt = _shamt;
58 let rd = 0, shamt = 0, Defs = [HI64, LO64] in {
71 let shamt = 0 in {
88 let shamt = 0;
|
| MipsInstrInfo.td | 145 def shamt : Operand<i32>;
205 // shamt field must fit in 5 bits.
271 let shamt = 0;
279 let shamt = 0;
296 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
302 let shamt = 0;
311 let shamt = 0;
318 FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rt, shamt:$shamt),
319 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 381 Constant *ShAmt = ConstantExpr::getZExt(COp1, TrOp->getType());
383 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
709 unsigned ShAmt = Op1C->getZExtValue();
714 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt), 0,
722 ComputeNumSignBits(I.getOperand(0), 0, &I) > ShAmt) {
752 unsigned ShAmt = Op1C->getZExtValue();
762 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
772 MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt),
796 unsigned ShAmt = Op1C->getZExtValue();
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 369 Constant *ShAmt = ConstantExpr::getZExt(Op1, TrOp->getType());
371 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
639 unsigned ShAmt = Op1C->getZExtValue();
644 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt))) {
651 ComputeNumSignBits(I.getOperand(0)) > ShAmt) {
678 unsigned ShAmt = Op1C->getZExtValue();
688 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
698 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
718 unsigned ShAmt = Op1C->getZExtValue();
744 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 661 unsigned ShAmt = SA->getZExtValue();
665 if (ShAmt >= BitWidth)
668 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
673 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
676 int Diff = ShAmt-C1;
690 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
700 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
703 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
707 TLO.DAG.getConstant(ShAmt, dl, ShTy))
[all...] |
