| /external/llvm/test/CodeGen/Hexagon/ |
| ashift-left-right.ll | 7 %shl1 = shl i32 16, %a
9 %ret = mul i32 %shl1, %shl2
17 %shl1 = ashr i32 16, %a
19 %ret = mul i32 %shl1, %shl2
|
| /external/llvm/test/CodeGen/Mips/ |
| micromips-shift.ll | 18 %shl1 = shl i32 %1, 10
19 store i32 %shl1, i32* @d, align 4
|
| /external/llvm/test/CodeGen/PowerPC/ |
| ldtoc-inv.ll | 23 %shl1 = shl i32 %0, %step_size
24 %idxprom2 = sext i32 %shl1 to i64
|
| ppc-shrink-wrapping.ll | 647 %shl1.i = shl i32 %or.i, 7
649 %or2.i = or i32 %shl1.i, %2
|
| /external/llvm/test/CodeGen/X86/ |
| targetLoweringGeneric.ll | 23 %shl1 = shl i32 %xor3, %i32In4
24 %sub1 = sub i32 %or2, %shl1
|
| legalize-shift-64.ll | 78 %shl1 = shl i64 1, %sh_prom
79 %cmp = icmp ne i64 %shl1, 4294967296
|
| sse2-vector-shifts.ll | 288 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
289 ret <4 x i32> %shl1
298 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
299 ret <4 x i32> %shl1
309 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
310 ret <4 x i32> %shl1
344 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
345 ret <4 x i32> %shl1
|
| vec_shift4.ll | 5 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
6 ; X32-LABEL: shl1:
14 ; X64-LABEL: shl1:
|
| mmx-coalescing.ll | 17 %shl1 = shl i32 %C, %B
|
| unused_stackslots.ll | 51 %shl1 = shl nsw i32 %rem, 3
52 %tmp9 = sext i32 %shl1 to i64
54 %tmp11 = or i32 %shl1, 4
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| vec_shift4.ll | 3 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| address-mode-opt.ll | 155 %shl1 = shl i32 %arg.int, 2
156 %addr.int = or i32 1, %shl1
168 %shl1 = shl i32 %arg.int, 2
169 %addr.int = or i32 5, %shl1
181 %shl1 = shl i32 %arg.int, 2
182 %addr.int = or i32 -1, %shl1
|
| /external/llvm/test/Transforms/InstCombine/ |
| nsw.ll | 31 ; CHECK-LABEL: @shl1(
34 define i64 @shl1(i64 %X, i64* %P) nounwind {
|
| bswap.ll | 133 %shl1 = and i32 %and2, 65280
134 %or = or i32 %and1, %shl1
|
| mul.ll | 254 ; CHECK: %[[shl1:.*]] = shl i32 1, %A
255 ; CHECK-NEXT: %[[shl2:.*]] = shl i32 %[[shl1]], %A
|
| rem.ll | 211 ; CHECK-NEXT: [[SHL1:%.*]] = shl i32 1, %x
213 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL1]], [[SHL2]]
214 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[AND]], [[SHL1]]
|
| shift.ll | 676 %shl1 = shl i32 1, %b
677 %shl2 = shl i32 %shl1, 2
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| nsw.ll | 31 ; CHECK: @shl1
34 define i64 @shl1(i64 %X, i64* %P) nounwind {
|
| shift.ll | 491 %shl1 = shl i32 1, %b
492 %shl2 = shl i32 %shl1, 2
|
| /art/test/538-checker-embed-constants/src/ |
| Main.java | 295 /// CHECK-START-ARM: long Main.shl1(long) disassembly (after)
299 /// CHECK-START-ARM: long Main.shl1(long) disassembly (after)
302 /// CHECK-START-X86: long Main.shl1(long) disassembly (after)
306 /// CHECK-START-X86: long Main.shl1(long) disassembly (after)
309 public static long shl1(long arg) { method in class:Main
689 assertLongEquals(shl1(longArg), 0x2468acf10eca8642L); method
695 assertLongEquals(shl1(~longArg), 0xdb97530ef13579bcL); method
|
| /art/compiler/optimizing/ |
| induction_var_analysis_test.cc | 567 HInstruction* shl1 = InsertInstruction( local
570 new (GetAllocator()) HAdd(DataType::Type::kInt32, shl1, constant100_), 0);
572 new (GetAllocator()) HSub(DataType::Type::kInt32, shl1, constant1_), 0);
576 new (GetAllocator()) HMul(DataType::Type::kInt32, shl1, constant2_), 0);
578 new (GetAllocator()) HShl(DataType::Type::kInt32, shl1, constant2_), 0);
579 k_header->AddInput(shl1);
584 EXPECT_STREQ("geo((2) * 2 ^ i + (0)):Int32", GetInductionInfo(shl1, 0).c_str());
789 HInstruction* shl1 = InsertInstruction( local
807 GetInductionInfo(shl1, 0).c_str());
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-bitfield-extract.ll | 309 %shl1 = shl i32 %or1, 2
310 store i32 %shl1, i32* %y, align 8
339 %shl1 = shl i64 %or1, 2
340 store i64 %shl1, i64* %y, align 8
|
| arm64-shrink-wrapping.ll | 653 %shl1 = shl i32 %a, %b
665 store i32 %shl1, i32* %ptr1
|
| /external/llvm/test/Transforms/Inline/ |
| inline_minisize.ll | 116 %shl1 = shl i32 %tmp3, 1
117 %add = add nsw i32 %shl1, 13
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/core/ |
| utils.h | 332 simd16scalari shl1 = _simd16_slli_epi32(cvt1, 8); local
336 simd16scalari dst = _simd16_or_si(_simd16_or_si(cvt0, shl1), _simd16_or_si(shl2, shl3));
391 simdscalari shl1 = _simd_slli_epi32(cvt1, 8); local
393 simdscalari dst = _simd_or_si(cvt0, shl1);
[all...] |
