| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/rx/ |
| mov.sm | 10 mov.B #{simm8},{dsp5}[{reg7}]
18 mov.W #{simm8},{mem}
|
| macros.inc | 10 macro simm8 {-128;127}
15 macro imm {{simm8};{simm16};{simm24};{simm32}}
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| epiphany-opc.c | 221 /* beq.s $simm8 */
224 { { MNEM, ' ', OP (SIMM8), 0 } },
233 /* bne.s $simm8 */
236 { { MNEM, ' ', OP (SIMM8), 0 } },
245 /* bgtu.s $simm8 */
248 { { MNEM, ' ', OP (SIMM8), 0 } },
257 /* bgteu.s $simm8 */
260 { { MNEM, ' ', OP (SIMM8), 0 } },
269 /* blteu.s $simm8 */
272 { { MNEM, ' ', OP (SIMM8), 0 } }
[all...] |
| m10300-opc.c | 179 #define SIMM8 (SD8N_SHIFT8+1)
183 #define SIMM16 (SIMM8+1)
450 { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
531 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
532 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
566 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
593 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
603 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
613 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
[all...] |
| m10200-opc.c | 121 #define SIMM8 (SD8N_PCREL+1)
125 #define SIMM16 (SIMM8+1)
167 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
247 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
250 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
254 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
275 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
|
| epiphany-desc.c | 410 { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
[all...] |
| m32r-opc.c | 270 /* addi $dr,$simm8 */
273 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
618 /* ldi8 $dr,$simm8 */
621 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
[all...] |
| m32r-opinst.c | 74 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
287 { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
[all...] |
| m32r-desc.c | 270 { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
341 /* simm8: 8 bit signed immediate */
342 { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
485 /* addi $dr,$simm8 */
775 /* ldi8 $dr,$simm8 */
[all...] |
| mep-desc.c | [all...] |
| mep-opc.c | [all...] |
| aarch64-opc.c | [all...] |
| /toolchain/binutils/binutils-2.27/cpu/ |
| epiphany.cpu | 150 (df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT
925 (name simm8)
929 (index f-simm8)
[all...] |
| m32r.cpu | 473 (df f-simm8 "simm8" () 8 8 INT #f #f)
668 ; be confusion between (f-)simm8 and (h-)simm8.
680 (dshpo simm8 "8 bit signed immediate" () h-sint f-simm8)
852 ;#.(string-append "addi " "$dr,$simm8") ; #. experiment
853 "addi $dr,$simm8"
854 (+ OP1_4 dr simm8)
855 (set dr (add dr simm8))
[all...] |
| fr30.cpu | 427 ; be confusion between (f-)simm8 and (h-)simm8.
[all...] |
| mep-core.cpu | 757 (dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW)
[all...] |
| ChangeLog | 129 (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
|
| frv.cpu | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZOperands.td | 186 def SIMM8 : SDNodeXForm<imm, [{
309 }], SIMM8, "S8Imm">;
402 }], SIMM8, "S8Imm">;
|
| /external/valgrind/VEX/priv/ |
| host_arm_defs.c | 3232 Int simm8; local
3279 Int simm8; local
[all...] |
| host_arm_isel.c | [all...] |
| guest_amd64_toIR.c | [all...] |
| guest_x86_toIR.c | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.td | 543 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
[all...] |
| /toolchain/binutils/binutils-2.27/bfd/ |
| xtensa-modules.c | [all...] |
