| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| aent.s | 6 sllv $2, $4, $6
12 sllv $2, $4, $6
|
| aent.d | 10 [0-9a-f]+ <foo[^>]*> sllv v0,a0,a2
12 [0-9a-f]+ <bar[^>]*> sllv v0,a0,a2
|
| rol.d | 12 0+0008 <[^>]*> sllv a0,a0,a1
16 0+0018 <[^>]*> sllv a0,a1,a2
26 0+0040 <[^>]*> sllv at,a0,at
30 0+0050 <[^>]*> sllv at,a1,at
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| shl.ll | 47 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
52 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
56 ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
68 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
73 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]]
77 ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]]
88 ; ALL: sllv $2, $4, $5
98 ; M2: sllv $[[T0:[0-9]+]], $5, $7
102 ; M2: sllv $[[T2:[0-9]+]], $4, $7
115 ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $
[all...] |
| /external/capstone/suite/MC/Mips/ |
| micromips-shift-instructions-EB.s.cs | 3 0x00,0x65,0x10,0x10 = sllv $2, $3, $5
|
| micromips-shift-instructions.s.cs | 3 0x65,0x00,0x10,0x10 = sllv $2, $3, $5
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/mips/ |
| anames.go | 106 "SLLV",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/mips/ |
| anames.go | 106 "SLLV",
|
| /external/llvm/test/MC/Mips/ |
| micromips-shift-instructions.s | 11 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
18 # CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10]
21 # CHECK-EL: sllv $2, $2, $3 # encoding: [0x43,0x00,0x10,0x10]
31 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
38 # CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
41 # CHECK-EB: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
48 sllv $2, $3, $5
|
| rotations32.s | 12 # CHECK-32: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
19 # CHECK-32: sllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x04]
52 # CHECK-32: sllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x04]
58 # CHECK-32: sllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x04]
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| vector-arith.ll | 268 ; MIPS32: sllv
269 ; MIPS32: sllv
270 ; MIPS32: sllv
271 ; MIPS32: sllv
272 ; MIPS32: sllv
273 ; MIPS32: sllv
274 ; MIPS32: sllv
275 ; MIPS32: sllv
276 ; MIPS32: sllv
277 ; MIPS32: sllv
[all...] |
| /prebuilts/go/darwin-x86/src/runtime/internal/atomic/ |
| asm_mips64x.s | 185 SLLV $3, R4
187 SLLV R4, R2
211 SLLV $3, R4
214 SLLV R4, R2
215 SLLV R4, R5
|
| /prebuilts/go/linux-x86/src/runtime/internal/atomic/ |
| asm_mips64x.s | 185 SLLV $3, R4
187 SLLV R4, R2
211 SLLV $3, R4
214 SLLV R4, R2
215 SLLV R4, R5
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| atomic.ll | 84 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
86 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
115 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
117 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
146 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
148 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
178 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
180 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
207 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
210 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| sll2.ll | 12 ; 16: sllv ${{[0-9]+}}, ${{[0-9]+}}
|
| atomic.ll | 140 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
142 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
185 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
187 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
230 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
232 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
276 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
278 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
318 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]
[all...] |
| /prebuilts/go/darwin-x86/src/runtime/ |
| rt0_linux_mips64x.s | 36 SLLV $32, RSB
|
| /prebuilts/go/linux-x86/src/runtime/ |
| rt0_linux_mips64x.s | 36 SLLV $32, RSB
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS64.rules | 74 (Lsh64x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
75 (Lsh64x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
76 (Lsh64x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
77 (Lsh64x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
79 (Lsh32x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
80 (Lsh32x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
81 (Lsh32x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
82 (Lsh32x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
84 (Lsh16x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
85 (Lsh16x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))
[all...] |
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| MIPS64.rules | 74 (Lsh64x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
75 (Lsh64x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
76 (Lsh64x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
77 (Lsh64x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
79 (Lsh32x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
80 (Lsh32x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
81 (Lsh32x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
82 (Lsh32x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
84 (Lsh16x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
85 (Lsh16x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))
[all...] |
| /external/valgrind/none/tests/mips32/ |
| MIPS32int.stdout.exp-mips32-BE | [all...] |
| MIPS32int.stdout.exp-mips32-LE | [all...] |
| /external/valgrind/none/tests/mips64/ |
| shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV,
170 case SLLV:
171 TEST1("sllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
173 TEST1("sllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
|
| /prebuilts/go/darwin-x86/src/runtime/cgo/ |
| asm_mips64x.s | 48 SLLV $32, RSB
|
| /prebuilts/go/linux-x86/src/runtime/cgo/ |
| asm_mips64x.s | 48 SLLV $32, RSB
|
