| /external/llvm/test/CodeGen/X86/ |
| sse41-intrinsics-x86.ll | 2 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
6 ; SSE41-LABEL: test_x86_sse41_blendvpd:
7 ; SSE41: ## BB#0:
8 ; SSE41-NEXT: movapd %xmm0, %xmm3
9 ; SSE41-NEXT: movaps %xmm2, %xmm0
10 ; SSE41-NEXT: blendvpd %xmm1, %xmm3
11 ; SSE41-NEXT: movapd %xmm3, %xmm0
12 ; SSE41-NEXT: retl
18 %res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1]
21 declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnon
[all...] |
| pr12312.ll | 1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx < %s | FileCheck %s --check-prefix SSE41
14 ; SSE41: veccond128
15 ; SSE41: ptest
16 ; SSE41: ret
32 ; SSE41: veccond256
33 ; SSE41: por
34 ; SSE41: ptest
35 ; SSE41: ret
51 ; SSE41: veccond512
52 ; SSE41: po
[all...] |
| vec_compare-sse4.ll | 3 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=-sse4.2,+sse4.1 | FileCheck %s --check-prefix=SSE41
22 ; SSE41-LABEL: test1:
23 ; SSE41: ## BB#0:
24 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
25 ; SSE41-NEXT: pxor %xmm2, %xmm1
26 ; SSE41-NEXT: pxor %xmm2, %xmm0
27 ; SSE41-NEXT: movdqa %xmm0, %xmm2
28 ; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
29 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
30 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm
[all...] |
| vec_floor.ll | 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
6 ; SSE41-LABEL: floor_v2f64:
7 ; SSE41: ## BB#0:
8 ; SSE41-NEXT: roundpd $9, %xmm0, %xmm0
9 ; SSE41-NEXT: retq
21 ; SSE41-LABEL: floor_v4f32:
22 ; SSE41: ## BB#0:
23 ; SSE41-NEXT: roundps $9, %xmm0, %xmm0
24 ; SSE41-NEXT: retq
36 ; SSE41-LABEL: floor_v4f64
[all...] |
| extract-store.ll | 1 ; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.1 | FileCheck %s -check-prefix=SSE41
7 ; SSE41: pextrb
9 ; SSE41-NOT: movb
18 ; SSE41: pextrw
20 ; SSE41-NOT: movw
29 ; SSE41-NOT: pextrb
31 ; SSE41-NOT: movb
40 ; SSE41-NOT: pextrw
42 ; SSE41-NOT: movw
|
| sse41-pmovxrm.ll | 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
6 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
7 ; SSE41: ## BB#0:
8 ; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
9 ; SSE41-NEXT: retq
22 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
23 ; SSE41: ## BB#0:
24 ; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
25 ; SSE41-NEXT: retq
38 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq
[all...] |
| vselect-2.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
12 ; SSE41-LABEL: test1:
13 ; SSE41: # BB#0:
14 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
15 ; SSE41-NEXT: retq
26 ; SSE41-LABEL: test2:
27 ; SSE41: # BB#0:
28 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
29 ; SSE41-NEXT: retq
41 ; SSE41-LABEL: test3
[all...] |
| vector-idiv-sdiv-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
34 ; SSE41-LABEL: test_div7_2i64:
35 ; SSE41: # BB#0:
36 ; SSE41-NEXT: pextrq $1, %xmm0, %rax
37 ; SSE41-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
38 ; SSE41-NEXT: imulq %rcx
39 ; SSE41-NEXT: movq %rdx, %rax
40 ; SSE41-NEXT: shrq $63, %rax
41 ; SSE41-NEXT: sarq %rdx
42 ; SSE41-NEXT: addq %rax, %rd
[all...] |
| vector-shuffle-sse41.ll | 2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE41
6 ; SSE41-LABEL: blend_packusdw:
7 ; SSE41: # BB#0:
8 ; SSE41-NEXT: packusdw %xmm2, %xmm0
9 ; SSE41-NEXT: retq
15 %p0 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
16 %p1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
22 ; SSE41-LABEL: blend_packuswb:
23 ; SSE41: # BB#0:
24 ; SSE41-NEXT: packuswb %xmm2, %xmm
[all...] |
| combine-sse41-intrinsics.ll | 5 %1 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 0)
14 %1 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 0)
23 %1 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i32 0)
32 %1 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 -1)
42 %1 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 -1)
52 %1 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i32 -1)
62 %1 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a0, i32 7)
71 %1 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a0, i32 7)
80 %1 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a0, i32 7)
88 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i32
[all...] |
| vector-idiv-udiv-128.ll | 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
36 ; SSE41-LABEL: test_div7_2i64:
37 ; SSE41: # BB#0:
38 ; SSE41-NEXT: pextrq $1, %xmm0, %rcx
39 ; SSE41-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
40 ; SSE41-NEXT: movq %rcx, %rax
41 ; SSE41-NEXT: mulq %rsi
42 ; SSE41-NEXT: subq %rdx, %rcx
43 ; SSE41-NEXT: shrq %rcx
44 ; SSE41-NEXT: addq %rdx, %rc
[all...] |
| vector-sext.ll | 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
10 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32-SSE41
25 ; SSE41-LABEL: sext_16i8_to_8i16:
26 ; SSE41: # BB#0: # %entry
27 ; SSE41-NEXT: pmovsxbw %xmm0, %xmm0
28 ; SSE41-NEXT: retq
35 ; X32-SSE41-LABEL: sext_16i8_to_8i16:
36 ; X32-SSE41: # BB#0: # %entry
37 ; X32-SSE41-NEXT: pmovsxbw %xmm0, %xmm0
38 ; X32-SSE41-NEXT: ret
[all...] |
| vector-blend.ll | 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
23 ; SSE41-LABEL: vsel_float:
24 ; SSE41: # BB#0: # %entry
25 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
26 ; SSE41-NEXT: retq
50 ; SSE41-LABEL: vsel_float2:
51 ; SSE41: # BB#0: # %entry
52 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
53 ; SSE41-NEXT: retq
77 ; SSE41-LABEL: vsel_4xi8
[all...] |
| promote-vec3.ll | 3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
28 ; SSE41-LABEL: zext_i8:
29 ; SSE41: # BB#0:
30 ; SSE41-NEXT: pxor %xmm0, %xmm0
31 ; SSE41-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
32 ; SSE41-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
33 ; SSE41-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
34 ; SSE41-NEXT: movd %xmm0, %eax
35 ; SSE41-NEXT: pextrw $2, %xmm0, %edx
36 ; SSE41-NEXT: pextrw $4, %xmm0, %ec
[all...] |
| /external/llvm/test/Bitcode/ |
| ptest-new.ll | 6 ; CHECK: call i32 @llvm.x86.sse41.ptestc(<2 x i64>
7 %res1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %bar, <2 x i64> %bar)
8 ; CHECK: call i32 @llvm.x86.sse41.ptestz(<2 x i64>
9 %res2 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %bar, <2 x i64> %bar)
10 ; CHECK: call i32 @llvm.x86.sse41.ptestnzc(<2 x i64>
11 %res3 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %bar, <2 x i64> %bar)
17 ; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) #1
18 ; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) #1
19 ; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) #1
21 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnon
[all...] |
| ptest-old.ll | 6 ; CHECK: call i32 @llvm.x86.sse41.ptestc(<2 x i64>
7 %res1 = call i32 @llvm.x86.sse41.ptestc(<4 x float> %bar, <4 x float> %bar)
8 ; CHECK: call i32 @llvm.x86.sse41.ptestz(<2 x i64>
9 %res2 = call i32 @llvm.x86.sse41.ptestz(<4 x float> %bar, <4 x float> %bar)
10 ; CHECK: call i32 @llvm.x86.sse41.ptestnzc(<2 x i64>
11 %res3 = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %bar, <4 x float> %bar)
17 ; CHECK: declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) #1
18 ; CHECK: declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) #1
19 ; CHECK: declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) #1
21 declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnon
[all...] |
| /external/skia/src/opts/ |
| SkOpts_sse41.cpp | 10 #define SK_OPTS_NS sse41
15 blit_row_s32a_opaque = sse41::blit_row_s32a_opaque;
|
| /external/skqp/src/opts/ |
| SkOpts_sse41.cpp | 10 #define SK_OPTS_NS sse41
15 blit_row_s32a_opaque = sse41::blit_row_s32a_opaque;
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| vec_compare-sse4.ll | 2 ; RUN: llc < %s -march=x86 -mattr=-sse42,+sse41 | FileCheck %s -check-prefix=SSE41
9 ; SSE41: test1:
10 ; SSE41-NOT: pcmpgtq
11 ; SSE41: ret
25 ; SSE41: test2:
26 ; SSE41: pcmpeqq
27 ; SSE41: ret
|
| peep-vector-extract-concat.ll | 1 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2,-sse41 | FileCheck %s
4 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2,-sse41 | FileCheck %s -check-prefix=WIN64
|
| vec_insert-3.ll | 1 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep punpcklqdq | count 1
|
| widen_cast-6.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse41 | FileCheck %s
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| sse-itoi.ll | 2 ; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse4.1 -cost-model -analyze < %s | FileCheck --check-prefix=SSE41 %s
8 ; SSE41: zext_v4i8_to_v4i64
9 ; SSE41: cost of 2 {{.*}} zext
21 ; SSE41: sext_v4i8_to_v4i64
22 ; SSE41: cost of 2 {{.*}} sext
34 ; SSE41: zext_v4i16_to_v4i64
35 ; SSE41: cost of 2 {{.*}} zext
47 ; SSE41: sext_v4i16_to_v4i64
48 ; SSE41: cost of 2 {{.*}} sext
61 ; SSE41: zext_v4i32_to_v4i6
[all...] |
| /external/skia/bench/ |
| pack_int_uint16_t_Bench.cpp | 19 * SSE41 added an int -> uint16_t pack instruction. (sse41)
22 * - sse41 < ssse3 <<< sse2_b < sse2_a;
23 * - the ssse3 version is only slightly slower than the sse41 version, maybe not at all
25 * - the ssse3 and sse41 versions are about 3x faster than either sse2 version
26 * - the sse41 version seems to cause some code generation trouble.
86 __m128i sse41(__m128i x) { function in namespace:__anon33800
90 DEF_BENCH( return new pack_int_uint16_t_Bench<sse41>("sse41"); )
|
| /external/skqp/bench/ |
| pack_int_uint16_t_Bench.cpp | 19 * SSE41 added an int -> uint16_t pack instruction. (sse41)
22 * - sse41 < ssse3 <<< sse2_b < sse2_a;
23 * - the ssse3 version is only slightly slower than the sse41 version, maybe not at all
25 * - the ssse3 and sse41 versions are about 3x faster than either sse2 version
26 * - the sse41 version seems to cause some code generation trouble.
86 __m128i sse41(__m128i x) { function in namespace:__anon34469
90 DEF_BENCH( return new pack_int_uint16_t_Bench<sse41>("sse41"); )
|
