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  /external/libxaac/decoder/armv8/
ixheaacd_cos_sin_mod_loop1.s 67 sshr v4.2d, v4.2d, #16
69 sshr v6.2d, v6.2d, #16
71 sshr v8.2d, v8.2d, #16
73 sshr v10.2d, v10.2d, #16
104 sshr v4.2d, v4.2d, #16
106 sshr v6.2d, v6.2d, #16
108 sshr v8.2d, v8.2d, #16
110 sshr v10.2d, v10.2d, #16
140 sshr v4.2d, v4.2d, #16
142 sshr v6.2d, v6.2d, #1
    [all...]
ixheaacd_cos_sin_mod_loop2.s 85 SSHR v4.2s, v4.2s, #1
104 sshr v4.2d, v4.2d, #16
106 sshr v6.2d, v6.2d, #16
108 sshr v8.2d, v8.2d, #16
110 sshr v10.2d, v10.2d, #16
144 sshr v4.2d, v4.2d, #16
146 sshr v6.2d, v6.2d, #16
148 sshr v8.2d, v8.2d, #16
150 sshr v10.2d, v10.2d, #16
183 sshr v4.2d, v4.2d, #1
    [all...]
ixheaacd_no_lap1.s 67 SSHR V23.4S, V24.4S, #16
84 SSHR V20.4S, V21.4S, #16
95 SSHR V23.4S, V24.4S, #16
112 SSHR V20.4S, V21.4S, #16
ixheaacd_overlap_add2.s 81 SSHR V23.4S, V23.4S, #16
104 SSHR V19.4S, V19.4S, #16
108 SSHR V23.4S, V23.4S, #16
147 SSHR V19.4S, V19.4S, #16
200 SSHR V23.4S, V23.4S, #16
214 SSHR V23.4S, V23.4S, #16
250 SSHR V19.4S, V19.4S, #16
256 SSHR V23.4S, V23.4S, #16
290 SSHR V19.4S, V19.4S, #16
ixheaacd_overlap_add1.s 111 SSHR V13.4S, V13.4S, #16
141 SSHR V9.4S, V9.4S, #16
207 SSHR V13.4S, V13.4S, #16
209 SSHR V9.4S, V9.4S, #16
265 SSHR V13.4S, V13.4S, #16
267 SSHR V9.4S, V9.4S, #16
312 SSHR V13.4S, V13.4S, #16
313 SSHR V9.4S, V9.4S, #16
ixheaacd_inv_dit_fft_8pt.s 106 SSHR v7.2d, v7.2d, #32 //tempr_q
107 SSHR v10.2d, v10.2d, #32 //tempi_q
128 SSHR v9.2d, v9.2d, #32
129 SSHR v13.2d, v13.2d, #32
ixheaacd_imdct_using_fft.s 333 SSHR v19.4S, v19.4S, #15
334 SSHR v18.4S, v18.4S, #15
349 SSHR v13.4S, v13.4S, #15
350 SSHR v14.4S, v14.4S, #15
655 SSHR v30.4S, v30.4S, #1
657 SSHR v31.4S, v31.4S, #1
682 SSHR v11.4S, v11.4S, #15
693 SSHR v12.4S, v12.4S, #15
694 SSHR v13.4S, v13.4S, #15
695 SSHR v14.4S, v14.4S, #1
    [all...]
ixheaacd_sbr_imdct_using_fft.s 286 SSHR V19.4S, V19.4S, #15
287 SSHR V18.4S, V18.4S, #15
300 SSHR V13.4S, V13.4S, #15
301 SSHR V14.4S, V14.4S, #15
628 SSHR V30.4S, V30.4S, #1
630 SSHR V31.4S, V31.4S, #1
654 SSHR V11.4S, V11.4S, #15
665 SSHR V12.4S, V12.4S, #15
666 SSHR V13.4S, V13.4S, #15
667 SSHR V14.4S, V14.4S, #1
    [all...]
ixheaacd_post_twiddle_overlap.s 271 sshR v8.2s, v8.2s, #16
450 sshR v24.4s, v24.4s, #16
452 sshR v26.4s, v26.4s, #16
453 sshR v0.4s, v0.4s, #16
686 sshR v14.4s, v14.4s, #16
695 sshR v6.4s, v6.4s, #16
739 sshR v30.4s, v30.4s, #16
748 sshR v22.4s, v22.4s, #16
865 sshR v24.4s, v24.4s, #16
867 sshR v26.4s, v26.4s, #1
    [all...]
ixheaacd_sbr_qmfsyn64_winadd.s 153 sshR v28.4s, v26.4s, #16
243 sshR v28.4s, v26.4s, #16
313 sshR v28.4s, v26.4s, #16
389 sshR v28.4s, v26.4s, #16
  /external/libhevc/common/arm64/
ihevc_intra_pred_luma_vert.s 233 sshr d24, d24,#8
236 sshr d25, d25,#8
243 sshr d24, d24,#8
246 sshr d25, d25,#8
268 sshr d24, d24,#8
271 sshr d25, d25,#8
281 sshr d24, d24,#8
284 sshr d25, d25,#8
298 sshr d24, d24,#8
301 sshr d25, d25,#
    [all...]
ihevc_intra_pred_luma_dc.s 138 sshr d7, d7,#32
257 sshr d3, d3,#8 //row 0 shift (prol) (first value to be ignored)
266 sshr d3, d3,#8 //row 1 shift (prol)
275 sshr d3, d3,#8 //row 2 shift (prol)
283 sshr d3, d3,#8 //row 3 shift (prol)
291 sshr d3, d3,#8 //row 4 shift (prol)
299 sshr d3, d3,#8 //row 5 shift (prol)
310 sshr d3, d3,#8 //row 6 shift (prol)
317 sshr d3, d3,#8 //row 7 shift (prol)
346 sshr d3, d3,#8 //row 9 shift (prol
    [all...]
ihevc_intra_pred_luma_horz.s 212 sshr v24.8h, v24.8h,#1
226 sshr v24.8h, v24.8h,#1
294 sshr v24.8h, v24.8h,#1
338 sshr v24.8h, v24.8h,#1
ihevc_intra_pred_chroma_horz.s 297 sshr v24.8h, v24.8h,#1
341 sshr v24.8h, v24.8h,#1
ihevc_intra_pred_filters_luma_mode_11_to_17.s 284 sshr v22.8h, v22.8h,#5
416 sshr v12.8h, v12.8h,#5
529 sshr v14.8h, v14.8h,#5
632 sshr v22.8h, v22.8h,#5
ihevc_intra_pred_luma_mode_3_to_9.s 164 sshr v22.8h, v22.8h,#5
296 sshr v12.8h, v12.8h,#5
408 sshr v14.8h, v14.8h,#5
503 sshr v22.8h, v22.8h,#5
  /external/llvm/test/CodeGen/AArch64/
div_minsize.ll 38 ; CHECK: sshr v1.8h, v0.8h, #15
40 ; CHECK: sshr v0.8h, v0.8h, #5
arm64-vselect.ll 9 ; sshr.4s v0, v0, #31
complex-int-to-fp.ll 34 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
55 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
93 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
112 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
149 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
arm64-vshr.ll 51 ; CHECK: sshr d0, d0, #63
arm64-neon-simd-shift.ll 5 ; CHECK: sshr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
12 ; CHECK: sshr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
19 ; CHECK: sshr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
26 ; CHECK: sshr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
33 ; CHECK: sshr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
40 ; CHECK: sshr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
47 ; CHECK: sshr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
  /external/libavc/common/armv8/
ih264_iquant_itrans_recon_av8.s 171 sshr v8.4h, v1.4h, #1 // d1>>1
172 sshr v9.4h, v3.4h, #1 // d3>>1
202 sshr v18.4h, v11.4h, #1 // q0>>1
203 sshr v19.4h, v13.4h, #1 // q1>>1
361 sshr v8.4h, v1.4h, #1 // d1>>1
362 sshr v9.4h, v3.4h, #1 // d3>>1
393 sshr v18.4h, v11.4h, #1 // q0>>1
394 sshr v19.4h, v13.4h, #1 // q1>>1
647 sshr v16.8h, v9.8h, #1 //(pi2_tmp_ptr[1] >> 1)
648 sshr v17.8h, v10.8h, #1 //(pi2_tmp_ptr[2] >> 1
    [all...]
  /external/capstone/suite/MC/AArch64/
neon-simd-shift.s.cs 2 0x20,0x04,0x0d,0x0f = sshr v0.8b, v1.8b, #3
3 0x20,0x04,0x1d,0x0f = sshr v0.4h, v1.4h, #3
4 0x20,0x04,0x3d,0x0f = sshr v0.2s, v1.2s, #3
5 0x20,0x04,0x0d,0x4f = sshr v0.16b, v1.16b, #3
6 0x20,0x04,0x1d,0x4f = sshr v0.8h, v1.8h, #3
7 0x20,0x04,0x3d,0x4f = sshr v0.4s, v1.4s, #3
8 0x20,0x04,0x7d,0x4f = sshr v0.2d, v1.2d, #3
neon-scalar-shift-imm.s.cs 2 0x0f,0x06,0x74,0x5f = sshr d15, d16, #12
  /external/llvm/test/MC/AArch64/
neon-simd-shift.s 8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
15 // CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f]
16 // CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f]
17 // CHECK: sshr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x0f
    [all...]

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