| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| ldst-reg-reg-offset.d | 28 50: 3c27cbe7 str b7, \[sp,w7,sxtw\]
29 54: 3c27dbe7 str b7, \[sp,w7,sxtw #0\]
30 58: 7c27cbe7 str h7, \[sp,w7,sxtw\]
31 5c: 7c27dbe7 str h7, \[sp,w7,sxtw #1\]
32 60: bc27cbe7 str s7, \[sp,w7,sxtw\]
33 64: bc27dbe7 str s7, \[sp,w7,sxtw #2\]
34 68: fc27cbe7 str d7, \[sp,w7,sxtw\]
35 6c: fc27dbe7 str d7, \[sp,w7,sxtw #3\]
36 70: 3ca7cbe7 str q7, \[sp,w7,sxtw\]
37 74: 3ca7dbe7 str q7, \[sp,w7,sxtw #4\
[all...] |
| ldst-reg-reg-offset.s | 46 .ifc \ext, sxtw
77 .irp ext, uxtw, lsl, sxtw, sxtx
93 ldr w1, [sp, wzr, sxtw #2]
94 str w1, [sp, wzr, sxtw #2]
|
| addsub.d | 45 94: 0b21c0f0 add w16, w7, w1, sxtw
46 98: 0b21c0f0 add w16, w7, w1, sxtw
47 9c: 0b21c4f0 add w16, w7, w1, sxtw #1
48 a0: 0b21c8f0 add w16, w7, w1, sxtw #2
49 a4: 0b21ccf0 add w16, w7, w1, sxtw #3
50 a8: 0b21d0f0 add w16, w7, w1, sxtw #4
99 16c: 0b21c3f0 add w16, wsp, w1, sxtw
100 170: 0b21c3f0 add w16, wsp, w1, sxtw
101 174: 0b21c7f0 add w16, wsp, w1, sxtw #1
102 178: 0b21cbf0 add w16, wsp, w1, sxtw #
[all...] |
| /external/libxaac/decoder/armv8/ |
| ixheaacd_fft32x32_ld2_armv8.s | 41 sxtw x2, w2
43 sxtw x3, w3
45 sxtw x4, w4
47 sxtw x5, w5
54 sxtw x2, w2
56 sxtw x3, w3
58 sxtw x4, w4
60 sxtw x5, w5
86 sxtw x2, w2
88 sxtw x3, w
[all...] |
| ixheaacd_cos_sin_mod_loop2.s | 53 sxtw x6, w6
61 sxtw x6, w6
63 sxtw x7, w7
68 sxtw x6, w6
80 // sxtw x6,w6
93 // sxtw x7,w7
96 sxtw x6, w6
99 sxtw x6, w6
135 sxtw x5, w5
137 sxtw x6, w
[all...] |
| ixheaacd_apply_scale_factors.s | 54 sxtw x4, w4
78 sxtw x5, w5
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-nvcast.ll | 7 ; CHECK: ldr s0, [x8, w1, sxtw #2]
21 ; CHECK: ldr s0, [x8, w1, sxtw #2]
|
| arm64-coalesce-ext.ll | 10 ; CHECK: sxtw x[[EXT:[0-9]+]], w[[SUM]]
|
| arm64-extend.ll | 8 ; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
|
| fast-isel-int-ext2.ll | 137 ; CHECK-NOT: sxtw
278 ; CHECK-NOT: sxtw
292 ; CHECK: ldrb w0, [x0, w1, sxtw]
307 ; CHECK: ldrh w0, [x0, w1, sxtw]
322 ; CHECK: ldrb w0, [x0, w1, sxtw]
337 ; CHECK: ldrh w0, [x0, w1, sxtw]
352 ; CHECK: ldr w0, [x0, w1, sxtw]
367 ; CHECK: ldrsb w0, [x0, w1, sxtw]
382 ; CHECK: ldrsh w0, [x0, w1, sxtw]
397 ; CHECK: ldrsb x0, [x0, w1, sxtw]
[all...] |
| ldst-regoffset.ll | 19 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]
47 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1]
71 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]
100 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]
124 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
152 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3]
174 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
200 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]
224 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
253 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3
[all...] |
| arm64-trunc-store.ll | 25 ; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2]
45 ; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1]
63 ; CHECK-NEXT: add [[ADDR:x[0-9]+]], [[BASEADDR]], w0, sxtw
|
| fast-isel-int-ext.ll | 44 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
55 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
113 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
124 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
252 ; CHECK-NOT: sxtw
363 ; CHECK-NOT: sxtw
374 ; CHECK: ldrb w0, [x0, w1, sxtw]
386 ; CHECK: ldrh w0, [x0, w1, sxtw]
398 ; CHECK: ldrb w0, [x0, w1, sxtw]
410 ; CHECK: ldrh w0, [x0, w1, sxtw]
[all...] |
| arm64-addr-type-promotion.ll | 15 ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], w0, sxtw]
16 ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw]
20 ; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], w1, sxtw
21 ; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], w0, sxtw
|
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 77 ldrb w1, [x3, w3, sxtw #4]
78 ldrh w1, [x3, w3, sxtw #4]
79 ldr w1, [x3, w3, sxtw #4]
80 ldr x1, [x3, w3, sxtw #4]
81 ldr b1, [x3, w3, sxtw #4]
82 ldr h1, [x3, w3, sxtw #4]
83 ldr s1, [x3, w3, sxtw #4]
84 ldr d1, [x3, w3, sxtw #4]
85 ldr q1, [x3, w3, sxtw #1]
87 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/disassembler/ |
| arm64_diassembler_test.cpp | 159 { 0xb87ed80f, "ldr w15, [x0, w30, sxtw #2]" },
160 { 0xb86fc9fe, "ldr w30, [x15, w15, sxtw #0]" },
168 { 0xb83ed80f, "str w15, [x0, w30, sxtw #2]" },
169 { 0xb82fc9fe, "str w30, [x15, w15, sxtw #0]" },
177 { 0x787ed80f, "ldrh w15, [x0, w30, sxtw #1]" },
178 { 0x786fc9fe, "ldrh w30, [x15, w15, sxtw #0]" },
186 { 0x783ed80f, "strh w15, [x0, w30, sxtw #1]" },
187 { 0x782fc9fe, "strh w30, [x15, w15, sxtw #0]" },
195 { 0x387ec80f, "ldrb w15, [x0, w30, sxtw ]" },
196 { 0x386fd9fe, "ldrb w30, [x15, w15, sxtw #0]" }
[all...] |
| /art/runtime/interpreter/mterp/arm64/ |
| op_packed_switch.S | 19 sxtw xINST, w0
|
| /external/libhevc/common/arm64/ |
| ihevc_deblk_chroma_vert.s | 62 sxtw x4,w4
63 sxtw x5,w5
64 sxtw x6,w6
98 sxtw x3,w3
114 sxtw x2,w2
147 sxtw x3,w3
163 sxtw x2,w2
|
| ihevc_deblk_chroma_horz.s | 61 sxtw x4,w4
62 sxtw x5,w5
63 sxtw x6,w6
65 sxtw x9,w9
|
| /external/libhevc/decoder/arm64/ |
| ihevcd_fmt_conv_420sp_to_420p.s | 96 sxtw x5,w5
103 sxtw x5,w5
144 sxtw x5,w5
146 sxtw x7,w7
158 sxtw x4,w4
|
| /external/llvm/test/CodeGen/Hexagon/ |
| extload-combine.ll | 30 ; CHECK: sxtw([[VAR1]])
52 ; CHECK: sxtw([[VAR3]])
74 ; CHECK: sxtw([[VAR5]])
|
| /external/libavc/common/armv8/ |
| ih264_inter_pred_luma_copy_av8.s | 85 sxtw x2, w2
86 sxtw x3, w3
87 sxtw x4, w4
88 sxtw x5, w5
243 sxtw x2, w2
244 sxtw x3, w3
|
| ih264_iquant_itrans_recon_dc_av8.s | 122 sxtw x3, w3
123 sxtw x4, w4
228 sxtw x3, w3
229 sxtw x4, w4
347 sxtw x3, w3
348 sxtw x4, w4
|
| /external/valgrind/none/tests/arm64/ |
| memory.c | 219 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
220 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0);
226 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
227 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
233 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
234 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
240 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
241 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
247 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
248 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0)
[all...] |
| /external/v8/src/regexp/arm64/ |
| regexp-macro-assembler-arm64.cc | 248 Operand(current_input_offset(), SXTW));
321 Operand(capture_start_offset, SXTW));
324 Operand(capture_length, SXTW));
327 Operand(current_input_offset(), SXTW));
331 Operand(capture_length, SXTW));
368 Operand(capture_length, SXTW));
371 __ Cmp(current_input_offset().X(), Operand(current_input_offset(), SXTW));
393 __ Add(x0, input_end(), Operand(capture_start_offset, SXTW));
397 __ Add(x1, input_end(), Operand(current_input_offset(), SXTW));
399 __ Sub(x1, x1, Operand(capture_length, SXTW));
[all...] |
