| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| ldst-reg-reg-offset.d | 38 78: 3c27ebe7 str b7, \[sp,x7,sxtx\]
39 7c: 3c27fbe7 str b7, \[sp,x7,sxtx #0\]
40 80: 7c27ebe7 str h7, \[sp,x7,sxtx\]
41 84: 7c27fbe7 str h7, \[sp,x7,sxtx #1\]
42 88: bc27ebe7 str s7, \[sp,x7,sxtx\]
43 8c: bc27fbe7 str s7, \[sp,x7,sxtx #2\]
44 90: fc27ebe7 str d7, \[sp,x7,sxtx\]
45 94: fc27fbe7 str d7, \[sp,x7,sxtx #3\]
46 98: 3ca7ebe7 str q7, \[sp,x7,sxtx\]
47 9c: 3ca7fbe7 str q7, \[sp,x7,sxtx #4\
[all...] |
| ldst-reg-reg-offset.s | 58 .ifc \ext, sxtx
77 .irp ext, uxtw, lsl, sxtw, sxtx
91 ldr x1, [sp, xzr, sxtx #3]
92 str x1, [sp, xzr, sxtx #3]
|
| addsub.d | 51 ac: 0b21e0f0 add w16, w7, w1, sxtx
52 b0: 0b21e0f0 add w16, w7, w1, sxtx
53 b4: 0b21e4f0 add w16, w7, w1, sxtx #1
54 b8: 0b21e8f0 add w16, w7, w1, sxtx #2
55 bc: 0b21ecf0 add w16, w7, w1, sxtx #3
56 c0: 0b21f0f0 add w16, w7, w1, sxtx #4
105 184: 0b21e3f0 add w16, wsp, w1, sxtx
106 188: 0b21e3f0 add w16, wsp, w1, sxtx
107 18c: 0b21e7f0 add w16, wsp, w1, sxtx #1
108 190: 0b21ebf0 add w16, wsp, w1, sxtx #
[all...] |
| addsub.s | 29 // or implicitly UXTX, SXTX or LSL; otherwise it Wm.
32 .ifnc \extend, SXTX
102 .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
|
| programmer-friendly.s | 44 // for all but the (possibly omitted) UXTX/LSL and SXTX
|
| shifted.d | 376 5c0: 8b23e041 add x1, x2, x3, sxtx
377 5c4: 8b23e441 add x1, x2, x3, sxtx #1
378 5c8: 8b23e841 add x1, x2, x3, sxtx #2
379 5cc: 8b23ec41 add x1, x2, x3, sxtx #3
380 5d0: 8b23f041 add x1, x2, x3, sxtx #4
475 74c: cb23e041 sub x1, x2, x3, sxtx
476 750: cb23e441 sub x1, x2, x3, sxtx #1
477 754: cb23e841 sub x1, x2, x3, sxtx #2
478 758: cb23ec41 sub x1, x2, x3, sxtx #3
479 75c: cb23f041 sub x1, x2, x3, sxtx #
[all...] |
| diagnostic.s | 66 ldrb w0, x1, x2, sxtx
67 prfm PLDL3KEEP, [x9, x15, sxtx #2]
|
| shifted.s | 123 op3_64x_more \op, sxtx
|
| /system/core/libpixelflinger/tests/arch-arm64/disassembler/ |
| arm64_diassembler_test.cpp | 162 { 0xb87febe0, "ldr w0, [sp, xzr, sxtx #0]" },
165 { 0xb860fbdf, "ldr wzr, [x30, x0, sxtx #2]" },
171 { 0xb83febe0, "str w0, [sp, xzr, sxtx #0]" },
174 { 0xb820fbdf, "str wzr, [x30, x0, sxtx #2]" },
180 { 0x787febe0, "ldrh w0, [sp, xzr, sxtx #0]" },
183 { 0x7860fbdf, "ldrh wzr, [x30, x0, sxtx #1]" },
189 { 0x783febe0, "strh w0, [sp, xzr, sxtx #0]" },
192 { 0x7820fbdf, "strh wzr, [x30, x0, sxtx #1]" },
198 { 0x387ffbe0, "ldrb w0, [sp, xzr, sxtx #0]" },
201 { 0x3860ebdf, "ldrb wzr, [x30, x0, sxtx ]" },
[all...] |
| /external/vixl/src/aarch64/ |
| operands-aarch64.cc | 321 // Extend modes SXTX and UXTX require a 64-bit register.
322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
342 (((extend_ == UXTX) || (extend_ == SXTX)) && (shift_amount_ == 0)));
407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
409 // SXTX extend mode requires a 64-bit offset register.
410 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX));
468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
469 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX)));
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/msp430/ |
| msp430x.s | 254 sxtx r2
255 sxtx.a &ede
256 sxtx.w r2
|
| /external/llvm/test/MC/AArch64/ |
| arm64-arithmetic-encoding.s | 177 add w1, w2, w3, sxtx
186 ; CHECK: add w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x0b]
221 sub w1, w2, w3, sxtx
230 ; CHECK: sub w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x4b]
265 adds w1, w2, w3, sxtx
274 ; CHECK: adds w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x2b]
283 adds x1, x2, w3, sxtx
292 ; CHECK: adds x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xab]
309 subs w1, w2, w3, sxtx
318 ; CHECK: subs w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x6b
[all...] |
| arm64-diags.s | 118 str d1, [x3, w3, sxtx #3]
119 ldr s1, [x3, d3, sxtx #2]
122 ; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
125 ; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
253 ; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
|
| basic-a64-diagnostics.s | 11 add w5, w7, x9, sxtx
12 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
19 // CHECK-ERROR: add w5, w7, x9, sxtx
32 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
187 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
190 // CHECK-ERROR-NEXT: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
193 // CHECK-ERROR-NEXT: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
212 // CHECK-ERROR-NEXT: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
218 // CHECK-ERROR-NEXT: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
224 // CHECK-ERROR-NEXT: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4
[all...] |
| basic-a64-instructions.s | 25 add x3, x5, x9, sxtx
33 // CHECK: add x3, x5, x9, sxtx // encoding: [0xa3,0xe0,0x29,0x8b]
43 add w2, w3, w5, sxtx
51 // CHECK: add w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x0b]
71 sub x3, x5, x9, sxtx
79 // CHECK: sub x3, x5, x9, sxtx // encoding: [0xa3,0xe0,0x29,0xcb]
88 sub w2, w3, w5, sxtx
96 // CHECK: sub w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x4b]
106 adds x3, x5, x9, sxtx #2
114 // CHECK: adds x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xab
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
| list7.go | 181 return fmt.Sprintf("R%d.SXTX<<%d", r&31, (r>>5)&7)
183 return fmt.Sprintf("R%d.SXTX", r&31)
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
| list7.go | 181 return fmt.Sprintf("R%d.SXTX<<%d", r&31, (r>>5)&7)
183 return fmt.Sprintf("R%d.SXTX", r&31)
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 48 SXTX,
67 case AArch64_AM::SXTX: return "sxtx";
134 case 7: return AArch64_AM::SXTX;
150 /// 111 ==> sxtx
161 case AArch64_AM::SXTX: return 7; break;
197 /// 111 ==> sxtx
|
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 351 // Extend modes SXTX and UXTX require a 64-bit register.
352 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
468 // SXTX extend mode requires a 64-bit offset register.
469 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
520 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.s | 37 ADDS R12.SXTX, R3, R1 // 61e02cab
43 CMN R1.SXTX<<2, R10 // 5fe921ab
256 CMP R22.SXTX, RSP // ffe336eb
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.s | 37 ADDS R12.SXTX, R3, R1 // 61e02cab
43 CMN R1.SXTX<<2, R10 // 5fe921ab
256 CMP R22.SXTX, RSP // ffe336eb
|
| /external/vixl/test/aarch64/ |
| test-api-aarch64.cc | 294 VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister());
306 VIXL_CHECK(!Operand(x6, SXTX, 2).IsPlainRegister());
|
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Disassembler.cpp | 206 "reserved","reserved", "sxtw", "sxtx"
215 "sxtb","sxth","sxtw","sxtx"
|
| /external/capstone/suite/MC/AArch64/ |
| basic-a64-instructions.s.cs | 9 0xa3,0xe0,0x29,0x8b = add x3, x5, x9, sxtx
17 0x62,0xe0,0x25,0x0b = add w2, w3, w5, sxtx
29 0xa3,0xe0,0x29,0xcb = sub x3, x5, x9, sxtx
37 0x62,0xe0,0x25,0x4b = sub w2, w3, w5, sxtx
45 0xa3,0xe8,0x29,0xab = adds x3, x5, x9, sxtx #2
53 0x62,0xe0,0x25,0x2b = adds w2, w3, w5, sxtx
61 0xa3,0xe8,0x29,0xeb = subs x3, x5, x9, sxtx #2
69 0x62,0xe0,0x25,0x6b = subs w2, w3, w5, sxtx
77 0xbf,0xe8,0x29,0xeb = cmp x5, x9, sxtx #2
85 0x7f,0xe0,0x25,0x6b = cmp w3, w5, sxtx
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-arithmetic.txt | 180 # CHECK: add w1, w2, w3, sxtx
222 # CHECK: sub w1, w2, w3, sxtx
264 # CHECK: adds w1, w2, w3, sxtx
302 # CHECK: subs w1, w2, w3, sxtx
|
