| /art/test/636-arm64-veneer-pool/ |
| info.txt | 1 Regression test for an issue with VIXL ARM64 veneer pools (b/34850123).
|
| /external/vixl/ |
| .gitreview | 4 project=arm/vixl
|
| README.version | 1 URL: https://github.com/armvixl/vixl/archive/1.7.tar.gz
|
| Android.bp | 28 // Copyright (c) 2016 VIXL authors
55 name: "vixl-common",
72 // Explicitly enable the write-strings warning. VIXL uses
92 name: "vixl-arm",
93 defaults: ["vixl-common"],
101 name: "vixl-arm64",
102 defaults: ["vixl-common"],
111 name: "vixl-debug",
112 defaults: ["vixl-common"],
123 name: "vixl-release"
[all...] |
| AUTHORS | 1 # Below is a list of people and organisations that have contributed to the VIXL
|
| Android.mk | 28 # Copyright (c) 2016 VIXL authors
56 vixl_timestamp := $(HOST_OUT_NATIVE_TESTS)/vixl-test-runner/test.timestamp
57 $(vixl_timestamp): $(HOST_OUT_NATIVE_TESTS)/vixl-test-runner/vixl-test-runner
58 # TODO: Once available, use the appropriate option of vixl-test-runner
59 # to point to the trace files instead of running from the vixl root.
60 echo Running vixl tests
63 echo vixl tests PASSED
66 .PHONY: run-vixl-tests
67 run-vixl-tests: $(vixl_timestamp
[all...] |
| README.md | 0 VIXL: ARMv8 Runtime Code Generation Library, Development Version
16 VIXL contains three components.
26 The VIXL git repository can be found [on 'https://git.linaro.org'][vixl].
28 Changes from previous versions of VIXL can be found in the
42 To build VIXL the following software is required:
48 A 64-bit host machine is required, implementing an LP64 data model. VIXL has
65 VIXL was developed for JavaScript engines so a number of features from A64 were
73 The VIXL simulator supports only those instructions that the VIXL assembler ca
[all...] |
| /art/compiler/optimizing/ |
| common_arm.h | 26 // TODO(VIXL): Make VIXL compile with -Wshadow.
39 static_assert(vixl::aarch32::kSpCode == SP, "vixl::aarch32::kSpCode must equal ART's SP");
41 inline dwarf::Reg DWARFReg(vixl::aarch32::Register reg) {
45 inline dwarf::Reg DWARFReg(vixl::aarch32::SRegister reg) {
49 inline vixl::aarch32::Register HighRegisterFrom(Location location) {
51 return vixl::aarch32::Register(location.AsRegisterPairHigh<vixl::aarch32::Register>());
54 inline vixl::aarch32::DRegister HighDRegisterFrom(Location location)
[all...] |
| common_arm64.h | 26 // TODO(VIXL): Make VIXL compile with -Wshadow.
42 // Convenience helpers to ease conversion to and from VIXL operands.
48 return vixl::aarch64::kSPRegInternalCode;
51 return vixl::aarch64::kZeroRegCode;
57 if (code == vixl::aarch64::kSPRegInternalCode) {
60 if (code == vixl::aarch64::kZeroRegCode) {
66 inline vixl::aarch64::Register XRegisterFrom(Location location) {
68 return vixl::aarch64::Register::GetXRegFromCode(VIXLRegCodeFromART(location.reg()));
71 inline vixl::aarch64::Register WRegisterFrom(Location location)
[all...] |
| code_generator_arm64.h | 31 // TODO(VIXL): Make VIXL compile with -Wshadow.
48 static constexpr int kMaxMacroInstructionSizeInBytes = 15 * vixl::aarch64::kInstructionSize;
51 static const vixl::aarch64::Register kParameterCoreRegisters[] = {
52 vixl::aarch64::x1,
53 vixl::aarch64::x2,
54 vixl::aarch64::x3,
55 vixl::aarch64::x4,
56 vixl::aarch64::x5,
57 vixl::aarch64::x6
[all...] |
| code_generator_arm_vixl.h | 30 // TODO(VIXL): make vixl clean wrt -Wshadow.
44 15 * vixl::aarch32::kMaxInstructionSizeInBytes;
46 static const vixl::aarch32::Register kParameterCoreRegistersVIXL[] = {
47 vixl::aarch32::r1,
48 vixl::aarch32::r2,
49 vixl::aarch32::r3
52 static const vixl::aarch32::SRegister kParameterFpuRegistersVIXL[] = {
53 vixl::aarch32::s0,
54 vixl::aarch32::s1
[all...] |
| /external/vixl/doc/aarch64/topics/ |
| index.md | 1 We will try to add documentation for topics that may be useful to VIXL users. If
3 us at <vixl@arm.com>.
8 * [Using VIM YouCompleteMe with VIXL](ycm.md)
|
| ycm.md | 1 VIM YouCompleteMe for VIXL
5 engine for VIM. VIXL includes a `.ycm_extra_conf.py` to configure YCM to work in
6 the VIXL repository.
|
| /external/vixl/test/ |
| test-runner.cc | 1 // Copyright 2014, VIXL authors
34 vixl::Test* vixl::Test::first_ = NULL;
35 vixl::Test* vixl::Test::last_ = NULL;
37 bool vixl::Test::verbose_ = false;
40 bool vixl::Test::debug_ = false;
43 bool vixl::Test::trace_sim_ = false;
44 bool vixl::Test::trace_reg_ = false;
45 bool vixl::Test::trace_write_ = false
[all...] |
| /art/compiler/utils/arm64/ |
| assembler_arm64.h | 32 // TODO(VIXL): Make VIXL compile with -Wshadow.
42 #define MEM_OP(...) vixl::aarch64::MemOperand(__VA_ARGS__)
70 vixl::aarch64::MacroAssembler* GetVIXLAssembler() { return &vixl_masm_; }
84 void SpillRegisters(vixl::aarch64::CPURegList registers, int offset);
85 void UnspillRegisters(vixl::aarch64::CPURegList registers, int offset);
95 void PoisonHeapReference(vixl::aarch64::Register reg);
97 void UnpoisonHeapReference(vixl::aarch64::Register reg);
99 void MaybePoisonHeapReference(vixl::aarch64::Register reg);
101 void MaybeUnpoisonHeapReference(vixl::aarch64::Register reg)
[all...] |
| managed_register_arm64_test.cc | 595 EXPECT_TRUE(vixl::aarch64::x0.Is(Arm64Assembler::reg_x(X0)));
596 EXPECT_TRUE(vixl::aarch64::x1.Is(Arm64Assembler::reg_x(X1)));
597 EXPECT_TRUE(vixl::aarch64::x2.Is(Arm64Assembler::reg_x(X2)));
598 EXPECT_TRUE(vixl::aarch64::x3.Is(Arm64Assembler::reg_x(X3)));
599 EXPECT_TRUE(vixl::aarch64::x4.Is(Arm64Assembler::reg_x(X4)));
600 EXPECT_TRUE(vixl::aarch64::x5.Is(Arm64Assembler::reg_x(X5)));
601 EXPECT_TRUE(vixl::aarch64::x6.Is(Arm64Assembler::reg_x(X6)));
602 EXPECT_TRUE(vixl::aarch64::x7.Is(Arm64Assembler::reg_x(X7)));
603 EXPECT_TRUE(vixl::aarch64::x8.Is(Arm64Assembler::reg_x(X8)));
604 EXPECT_TRUE(vixl::aarch64::x9.Is(Arm64Assembler::reg_x(X9)))
[all...] |
| /art/test/635-checker-arm64-volatile-load-cc/ |
| info.txt | 1 Regression test checking that the VIXL ARM64 scratch register pool is
|
| /art/test/646-checker-arraycopy-large-cst-pos/ |
| info.txt | 1 Regression test for an issue with a depleted VIXL scratch register
|
| /art/disassembler/ |
| disassembler_arm64.h | 22 // TODO(VIXL): Make VIXL compile with -Wshadow.
32 class CustomDisassembler FINAL : public vixl::aarch64::Disassembler {
35 : vixl::aarch64::Disassembler(),
42 reinterpret_cast<const vixl::aarch64::Instruction*>(options->base_address_));
47 void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
48 const vixl::aarch64::CPURegister& reg) OVERRIDE;
51 void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE;
54 void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE;
83 vixl::aarch64::Decoder decoder
[all...] |
| /art/simulator/ |
| code_simulator_arm64.h | 22 // TODO(VIXL): Make VIXL compile with -Wshadow.
48 vixl::aarch64::Decoder* decoder_;
49 vixl::aarch64::Simulator* simulator_;
|
| /prebuilts/abi-dumps/vndk/28/32/arm_armv7-a-neon/source-based/ |
| libvixl-arm64.so.lsdump.gz | |
| /prebuilts/abi-dumps/vndk/28/64/arm64_armv8-a/source-based/ |
| libvixl-arm64.so.lsdump.gz | |
| /prebuilts/abi-dumps/vndk/28/64/arm_armv8-a/source-based/ |
| libvixl-arm64.so.lsdump.gz | |
| /prebuilts/abi-dumps/vndk/28/32/x86/source-based/ |
| libvixl-arm64.so.lsdump.gz | |
| /prebuilts/abi-dumps/vndk/28/64/x86/source-based/ |
| libvixl-arm64.so.lsdump.gz | |
