| /external/llvm/test/MC/ARM/ |
| neon-mul-encoding.s | 3 vmul.i8 d16, d16, d17
4 vmul.i16 d16, d16, d17
5 vmul.i32 d16, d16, d17
6 vmul.f32 d16, d16, d17
7 vmul.i8 q8, q8, q9
8 vmul.i16 q8, q8, q9
9 vmul.i32 q8, q8, q9
10 vmul.f32 q8, q8, q9
11 vmul.p8 d16, d16, d17
12 vmul.p8 q8, q8, q
[all...] |
| neont2-mul-encoding.s | 5 vmul.i8 d16, d16, d17
6 vmul.i16 d16, d16, d17
7 vmul.i32 d16, d16, d17
8 vmul.f32 d16, d16, d17
9 vmul.i8 q8, q8, q9
10 vmul.i16 q8, q8, q9
11 vmul.i32 q8, q8, q9
12 vmul.f32 q8, q8, q9
13 vmul.p8 d16, d16, d17
14 vmul.p8 q8, q8, q
[all...] |
| /external/capstone/suite/MC/ARM/ |
| neon-mul-encoding.s.cs | 2 0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17
3 0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17
4 0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17
5 0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17
6 0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9
7 0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9
8 0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9
9 0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9
10 0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17
11 0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q
[all...] |
| neont2-mul-encoding.s.cs | 2 0x40,0xef,0xb1,0x09 = vmul.i8 d16, d16, d17
3 0x50,0xef,0xb1,0x09 = vmul.i16 d16, d16, d17
4 0x60,0xef,0xb1,0x09 = vmul.i32 d16, d16, d17
5 0x40,0xff,0xb1,0x0d = vmul.f32 d16, d16, d17
6 0x40,0xef,0xf2,0x09 = vmul.i8 q8, q8, q9
7 0x50,0xef,0xf2,0x09 = vmul.i16 q8, q8, q9
8 0x60,0xef,0xf2,0x09 = vmul.i32 q8, q8, q9
9 0x40,0xff,0xf2,0x0d = vmul.f32 q8, q8, q9
10 0x40,0xff,0xb1,0x09 = vmul.p8 d16, d16, d17
11 0x40,0xff,0xf2,0x09 = vmul.p8 q8, q8, q
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| fmuls.ll | 13 ; VFP2: vmul.f32 s0, s1, s0
16 ; NFP1: vmul.f32 d0, d1, d0
18 ; NFP0: vmul.f32 s0, s1, s0
21 ; CORTEXA8: vmul.f32 d0, d1, d0
23 ; CORTEXA9: vmul.f32 s{{.}}, s{{.}}, s{{.}}
|
| fmacs.ll | 16 ; A8: vmul.f32
32 ; A8: vmul.f64
48 ; A8: vmul.f32
60 ; A8: vmul.f32
61 ; A8: vmul.f32
85 ; A8: vmul.f32
86 ; A8: vmul.f32
92 ; A9: vmul.f32
97 ; HARD: vmul.f32 s0, s2, s3
|
| fnmul.ll | 2 ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep vmul.f64
|
| fmscs.ll | 14 ; A8: vmul.f32
30 ; A8: vmul.f64
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neont2-mul-encoding.s | 5 @ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x09]
6 vmul.i8 d16, d16, d17
7 @ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09]
8 vmul.i16 d16, d16, d17
9 @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09]
10 vmul.i32 d16, d16, d17
11 @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d]
12 vmul.f32 d16, d16, d17
13 @ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x09]
14 vmul.i8 q8, q8, q
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| fmuls.ll | 26 ; VFP2: vmul.f32 s
29 ; NFP1: vmul.f32 d
31 ; NFP0: vmul.f32 s
34 ; CORTEXA8: vmul.f32 s
36 ; CORTEXA8U: vmul.f32 d
38 ; CORTEXA9: vmul.f32 s
|
| neon-spfp.ll | 19 ; This test makes sure we're not lowering VMUL.f32 D* (aka. NEON) for single-prec. FP ops, since
47 ; CHECK-LINUXA5: vmul.f32 s{{[0-9]*}}
48 ; CHECK-LINUXA8: vmul.f32 s{{[0-9]*}}
49 ; CHECK-LINUXA9: vmul.f32 s{{[0-9]*}}
50 ; CHECK-LINUXA15: vmul.f32 s{{[0-9]*}}
52 ; CHECK-LINUXSWIFT: vmul.f32 d{{[0-9]*}}
54 ; CHECK-UNSAFEA5: vmul.f32 d{{[0-9]*}}
55 ; CHECK-UNSAFEA8: vmul.f32 d{{[0-9]*}}
57 ; CHECK-UNSAFEA9: vmul.f32 s{{[0-9]*}}
58 ; CHECK-UNSAFEA15: vmul.f32 s{{[0-9]*}
[all...] |
| fp-fast.ll | 7 ; CHECK: vmul.f32
16 ; CHECK-NOT: vmul
18 ; CHECK-NOT: vmul
45 ; CHECK: vmul.f32
54 ; CHECK: vmul.f32
|
| no-fpu.ll | 26 ; NONEON-NOVFP-NOT: vmul.f64
28 ; NOVFP-NOT: vmul.f64
30 ; NONEON-VFP: vmul.f64
|
| fmacs.ll | 16 ; A8: vmul.f32
32 ; A8: vmul.f64
48 ; A8: vmul.f32
60 ; A8: vmul.f32
61 ; A8: vmul.f32
85 ; A8: vmul.f32
86 ; A8: vmul.f32
92 ; A9: vmul.f32
97 ; HARD: vmul.f32 s0, s2, s3
|
| fmscs.ll | 14 ; A8: vmul.f32
30 ; A8: vmul.f64
|
| fnmacs.ll | 14 ; A8: vmul.f32
30 ; A8: vmul.f64
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| simd_by_scalar_low_regbank.d | 1 #name: VMUL/VMLA/VMLS by scalar reg restriction
|
| simd_by_scalar_low_regbank.s | 2 .irp op, vmul.i16 vmul.f16 vmul.i32 vmul.f32
|
| simd_by_scalar_low_regbank_thumb.d | 1 #name: VMUL/VMLA/VMLS by scalar reg restriction (Thumb)
|
| simd_by_scalar_low_regbank.l | 2 [^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.i32 d3,d12,d7\[2\]'
3 [^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.i32 q3,q12,d7\[2\]'
4 [^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.f32 d3,d12,d7\[2\]'
5 [^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.f32 q3,q12,d7\[2\]'
6 [^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.i16 d4,d9,d8\[1\]'
7 [^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.i16 q4,q9,d8\[1\]'
8 [^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.f16 d4,d9,d8\[1\]'
9 [^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.f16 q4,q9,d8\[1\]'
10 [^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i16 d13,d6,d15\[3\]'
11 [^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i16 q13,q6,d15\[3\]
[all...] |
| neon-psyn.s | 9 vmul fish.s16, fish.s16, fish.s16
11 vmul banana, banana, cow.s32
12 vmul d3.s32, d3.s32, d2.s32
|
| /external/llvm/test/CodeGen/Thumb2/ |
| cortex-fp.ll | 11 ; CORTEXM4: vmul.f32 s
12 ; CORTEXM7: vmul.f32 s
13 ; CORTEXA8: vmul.f32 d
24 ; CORTEXM7: vmul.f64 d
25 ; CORTEXA8: vmul.f64 d
|
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| mul-vec.ll | 1 ; Show that we know how to translate vmul vector instructions.
35 ; ASM: vmul.f32 q10, q10, q11
37 ; IASM-NOT: vmul.f32
50 ; ASM: vmul.i32 q10, q10, q11
52 ; IASM-NOT: vmul.i32
65 ; ASM: vmul.i16 q10, q10, q11
67 ; IASM-NOT: vmul.i16
80 ; ASM: vmul.i8 q10, q10, q11
82 ; IASM-NOT: vmul.i8
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| cortex-fp.ll | 10 ; CORTEXM4: vmul.f32 s0, s1, s0
11 ; CORTEXA8: vmul.f32 d0, d1, d0
22 ; CORTEXA8: vmul.f64 d16, d17, d16
|
| /external/gemmlowp/meta/ |
| transform_kernels_arm_32.h | 63 "vmul.f32 q0, q0, q7\n"
64 "vmul.f32 q1, q1, q7\n"
65 "vmul.f32 q2, q2, q7\n"
66 "vmul.f32 q3, q3, q7\n"
71 "vmul.f32 q0, q0, q8\n"
72 "vmul.f32 q1, q1, q8\n"
73 "vmul.f32 q2, q2, q8\n"
74 "vmul.f32 q3, q3, q8\n"
142 "vmul.f32 q0, q0, q7\n"
143 "vmul.f32 q1, q1, q7\n
[all...] |
