| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv8-a+simd.s | 32 vrintm.f32 d15, d15
38 vrintm.f32 q7, q7
70 vrintm.f32 d15, d15
76 vrintm.f32 q7, q7
|
| armv7e-m+fpv5-sp-d16.s | 29 vrintm.f32 s31, s31
|
| armv7e-m+fpv5-d16.s | 45 vrintm.f32 s31, s31
52 vrintm.f64 d10, d10
|
| armv8-a+fp.s | 45 vrintm.f32 s31, s31
52 vrintm.f64 d31, d31
101 vrintm.f32 s31, s31
108 vrintm.f64 d31, d31
|
| armv8-a+simd.d | 34 0[0-9a-f]+ <[^>]+> f3baf68f vrintm.f32 d15, d15
40 0[0-9a-f]+ <[^>]+> f3bae6ce vrintm.f32 q7, q7
70 0[0-9a-f]+ <[^>]+> ffba f68f vrintm.f32 d15, d15
76 0[0-9a-f]+ <[^>]+> ffba e6ce vrintm.f32 q7, q7
|
| armv7e-m+fpv5-sp-d16.d | 29 0[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32 s31, s31
|
| armv8-2-fp16-scalar.s | 50 .irp op, vrinta.f16, vrintm.f16, vrintn.f16, vrintp.f16, vrintr.f16, vrintx.f16, vrintz.f16
|
| armv8-a+fp.d | 46 0[0-9a-f]+ <[^>]+> fefbfa6f vrintm.f32 s31, s31
53 0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64 d31, d31
100 0[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32 s31, s31
107 0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64 d31, d31
|
| /external/llvm/test/MC/ARM/ |
| neon-v8.s | 64 vrintm.f32 d3, d0
65 @ CHECK: vrintm.f32 d3, d0 @ encoding: [0x80,0x36,0xba,0xf3]
66 vrintm.f32 q1, q4
67 @ CHECK: vrintm.f32 q1, q4 @ encoding: [0xc8,0x26,0xba,0xf3]
|
| thumb-neon-v8.s | 64 vrintm.f32 d3, d0
65 @ CHECK: vrintm.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x36]
66 vrintm.f32 q1, q4
67 @ CHECK: vrintm.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x26]
|
| directive-arch_extension-fp.s | 139 vrintm.f32 s0, s0
141 vrintm.f64 d0, d0
143 vrintm.f32.f32 s0, s0
145 vrintm.f64.f64 d0, d0
275 vrintm.f32 s0, s0
277 vrintm.f64 d0, d0
279 vrintm.f32.f32 s0, s0
281 vrintm.f64.f64 d0, d0
|
| directive-arch_extension-simd.s | 111 vrintm.f32 s0, s0
113 vrintm.f64 d0, d0
115 vrintm.f32.f32 s0, s0
117 vrintm.f64.f64 d0, d0
219 vrintm.f32 s0, s0
221 vrintm.f64 d0, d0
223 vrintm.f32.f32 s0, s0
225 vrintm.f64.f64 d0, d0
|
| fp-armv8.s | 121 vrintm.f64 d3, d4
122 @ CHECK: vrintm.f64 d3, d4 @ encoding: [0x44,0x3b,0xbb,0xfe]
123 vrintm.f32 s12, s1
124 @ CHECK: vrintm.f32 s12, s1 @ encoding: [0x60,0x6a,0xbb,0xfe]
|
| thumb-fp-armv8.s | 127 vrintm.f64 d3, d4
128 @ CHECK: vrintm.f64 d3, d4 @ encoding: [0xbb,0xfe,0x44,0x3b]
129 vrintm.f32 s12, s1
130 @ CHECK: vrintm.f32 s12, s1 @ encoding: [0xbb,0xfe,0x60,0x6a]
|
| invalid-fp-armv8.s | 89 @ V8: error: instruction 'vrintm' is not predicable, but condition code specified
|
| invalid-neon-v8.s | 26 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified
|
| /external/capstone/suite/MC/ARM/ |
| neon-v8.s.cs | 30 0x80,0x36,0xba,0xf3 = vrintm.f32 d3, d0
31 0xc8,0x26,0xba,0xf3 = vrintm.f32 q1, q4
|
| thumb-neon-v8.s.cs | 30 0xba,0xff,0x80,0x36 = vrintm.f32 d3, d0
31 0xba,0xff,0xc8,0x26 = vrintm.f32 q1, q4
|
| fp-armv8.s.cs | 50 0x44,0x3b,0xbb,0xfe = vrintm.f64 d3, d4
51 0x60,0x6a,0xbb,0xfe = vrintm.f32 s12, s1
|
| thumb-fp-armv8.s.cs | 50 0xbb,0xfe,0x44,0x3b = vrintm.f64 d3, d4
51 0xbb,0xfe,0x60,0x6a = vrintm.f32 s12, s1
|
| /external/llvm/test/CodeGen/ARM/ |
| arm32-rounding.ll | 6 ; CHECK: vrintm.f32
15 ; DP: vrintm.f64
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| neon-v8.txt | 65 # CHECK: vrintm.f32 d3, d0
67 # CHECK: vrintm.f32 q1, q4
|
| thumb-neon-v8.txt | 65 # CHECK: vrintm.f32 d3, d0
67 # CHECK: vrintm.f32 q1, q4
|
| fp-armv8.txt | 152 # CHECK: vrintm.f64 d3, d4
155 # CHECK: vrintm.f32 s12, s1
|
| thumb-fp-armv8.txt | 160 # CHECK: vrintm.f64 d3, d4
163 # CHECK: vrintm.f32 s12, s1
|
