1 /** @file 2 3 Copyright (c) 2013-2015 Intel Corporation. 4 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 **/ 15 16 #ifndef _SPI_FLASH_DEVICE_H_ 17 #define _SPI_FLASH_DEVICE_H_ 18 19 #include <PiDxe.h> 20 #include <Protocol/Spi.h> 21 #include <Protocol/FirmwareVolumeBlock.h> 22 23 // 24 // Supported SPI Flash Devices 25 // 26 typedef enum { 27 EnumSpiFlash25L3205D, // Macronix 32Mbit part 28 EnumSpiFlashW25Q32, // Winbond 32Mbit part 29 EnumSpiFlashW25X32, // Winbond 32Mbit part 30 EnumSpiFlashAT25DF321, // Atmel 32Mbit part 31 EnumSpiFlashQH25F320, // Intel 32Mbit part 32 EnumSpiFlash25VF064C, // SST 64Mbit part 33 EnumSpiFlashM25PX64, // NUMONYX 64Mbit part 34 EnumSpiFlashAT25DF641, // Atmel 64Mbit part 35 EnumSpiFlashS25FL064K, // Spansion 64Mbit part 36 EnumSpiFlash25L6405D, // Macronix 64Mbit part 37 EnumSpiFlashW25Q64, // Winbond 64Mbit part 38 EnumSpiFlashW25X64, // Winbond 64Mbit part 39 EnumSpiFlashQH25F640, // Intel 64Mbit part 40 EnumSpiFlashMax 41 } SPI_FLASH_TYPES_SUPPORTED; 42 43 // 44 // Flash Device commands 45 // 46 // If a supported device uses a command different from the list below, a device specific command 47 // will be defined just below it's JEDEC id section. 48 // 49 #define SPI_COMMAND_WRITE 0x02 50 #define SPI_COMMAND_WRITE_AAI 0xAD 51 #define SPI_COMMAND_READ 0x03 52 #define SPI_COMMAND_ERASE 0x20 53 #define SPI_COMMAND_WRITE_DISABLE 0x04 54 #define SPI_COMMAND_READ_S 0x05 55 #define SPI_COMMAND_WRITE_ENABLE 0x06 56 #define SPI_COMMAND_READ_ID 0xAB 57 #define SPI_COMMAND_JEDEC_ID 0x9F 58 #define SPI_COMMAND_WRITE_S_EN 0x50 59 #define SPI_COMMAND_WRITE_S 0x01 60 #define SPI_COMMAND_CHIP_ERASE 0xC7 61 #define SPI_COMMAND_BLOCK_ERASE 0xD8 62 63 // 64 // Flash JEDEC device ids 65 // 66 // SST 8Mbit part 67 // 68 #define SPI_SST25VF080B_ID1 0xBF 69 #define SPI_SST25VF080B_ID2 0x25 70 #define SPI_SST25VF080B_ID3 0x8E 71 // 72 // SST 16Mbit part 73 // 74 #define SPI_SST25VF016B_ID1 0xBF 75 #define SPI_SST25VF016B_ID2 0x25 76 #define SPI_SST25V016BF_ID3 0x41 77 // 78 // Macronix 32Mbit part 79 // 80 // MX25 part does not support WRITE_AAI comand (0xAD) 81 // 82 #define SPI_MX25L3205_ID1 0xC2 83 #define SPI_MX25L3205_ID2 0x20 84 #define SPI_MX25L3205_ID3 0x16 85 // 86 // Intel 32Mbit part bottom boot 87 // 88 #define SPI_QH25F320_ID1 0x89 89 #define SPI_QH25F320_ID2 0x89 90 #define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot 91 // 92 // Intel 64Mbit part bottom boot 93 // 94 #define SPI_QH25F640_ID1 0x89 95 #define SPI_QH25F640_ID2 0x89 96 #define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot 97 // 98 // QH part does not support command 0x20 for erase; only 0xD8 (sector erase) 99 // QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part) 100 // 0x40 command ignored if address outside of parameter block range 101 // 102 #define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40 103 // 104 // Winbond 32Mbit part 105 // 106 #define SPI_W25X32_ID1 0xEF 107 #define SPI_W25X32_ID2 0x30 // Memory Type 108 #define SPI_W25X32_ID3 0x16 // Capacity 109 #define SF_DEVICE_ID1_W25Q32 0x16 110 111 // 112 // Winbond 64Mbit part 113 // 114 #define SPI_W25X64_ID1 0xEF 115 #define SPI_W25X64_ID2 0x30 // Memory Type 116 #define SPI_W25X64_ID3 0x17 // Capacity 117 #define SF_DEVICE_ID0_W25QXX 0x40 118 #define SF_DEVICE_ID1_W25Q64 0x17 119 // 120 // Winbond 128Mbit part 121 // 122 #define SF_DEVICE_ID0_W25Q128 0x40 123 #define SF_DEVICE_ID1_W25Q128 0x18 124 125 // 126 // Atmel 32Mbit part 127 // 128 #define SPI_AT26DF321_ID1 0x1F 129 #define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density 130 #define SPI_AT26DF321_ID3 0x00 131 132 #define SF_VENDOR_ID_ATMEL 0x1F 133 #define SF_DEVICE_ID0_AT25DF641 0x48 134 #define SF_DEVICE_ID1_AT25DF641 0x00 135 136 // 137 // SST 8Mbit part 138 // 139 #define SPI_SST25VF080B_ID1 0xBF 140 #define SPI_SST25VF080B_ID2 0x25 141 #define SPI_SST25VF080B_ID3 0x8E 142 #define SF_DEVICE_ID0_25VF064C 0x25 143 #define SF_DEVICE_ID1_25VF064C 0x4B 144 145 // 146 // SST 16Mbit part 147 // 148 #define SPI_SST25VF016B_ID1 0xBF 149 #define SPI_SST25VF016B_ID2 0x25 150 #define SPI_SST25V016BF_ID3 0x41 151 152 // 153 // Winbond 32Mbit part 154 // 155 #define SPI_W25X32_ID1 0xEF 156 #define SPI_W25X32_ID2 0x30 // Memory Type 157 #define SPI_W25X32_ID3 0x16 // Capacity 158 159 #define SF_VENDOR_ID_MX 0xC2 160 #define SF_DEVICE_ID0_25L6405D 0x20 161 #define SF_DEVICE_ID1_25L6405D 0x17 162 163 #define SF_VENDOR_ID_NUMONYX 0x20 164 #define SF_DEVICE_ID0_M25PX64 0x71 165 #define SF_DEVICE_ID1_M25PX64 0x17 166 167 // 168 // Spansion 64Mbit part 169 // 170 #define SF_VENDOR_ID_SPANSION 0xEF 171 #define SF_DEVICE_ID0_S25FL064K 0x40 172 #define SF_DEVICE_ID1_S25FL064K 0x00 173 174 // 175 // index for prefix opcodes 176 // 177 #define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE 178 #define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN 179 #define BIOS_CTRL 0xDC 180 181 #define PFAB_CARD_DEVICE_ID 0x5150 182 #define PFAB_CARD_VENDOR_ID 0x8086 183 #define PFAB_CARD_SETUP_REGISTER 0x40 184 #define PFAB_CARD_SETUP_BYTE 0x0d 185 186 187 #endif 188
