1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following form: 28 // MNEMONIC{<c>}.W <Rd>, PC, #<imm8> ; wide encoding 29 30 { 31 "mnemonics" : [ 32 "Add" // ADD{<c>}{<q>} <Rd>, PC, #<imm8> ; T1 33 ], 34 "description" : { 35 "operands": [ 36 { 37 "name": "cond", 38 "type": "Always" 39 }, 40 { 41 "name": "rd", 42 "type": "LowRegisters" 43 }, 44 { 45 "name": "rn", 46 "type": "RegisterPC" 47 }, 48 { 49 "name": "op", 50 "wrapper": "Operand", 51 "operands": [ 52 { 53 "name": "immediate", 54 "type": "OffsetLowerThan256" 55 } 56 ] 57 } 58 ], 59 "inputs": [] 60 }, 61 "test-files": [ 62 { 63 "type": "assembler", 64 "test-cases": [ 65 { 66 "name": "Operands", 67 "operands": [ 68 "rd", "rn", "immediate" 69 ], 70 "operand-limit": 1000 71 } 72 ] 73 } 74 ] 75 } 76
