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      1 // i386 register table.
      2 // Copyright (C) 2007-2016 Free Software Foundation, Inc.
      3 //
      4 // This file is part of the GNU opcodes library.
      5 //
      6 // This library is free software; you can redistribute it and/or modify
      7 // it under the terms of the GNU General Public License as published by
      8 // the Free Software Foundation; either version 3, or (at your option)
      9 // any later version.
     10 //
     11 // It is distributed in the hope that it will be useful, but WITHOUT
     12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     13 // or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     14 // License for more details.
     15 //
     16 // You should have received a copy of the GNU General Public License
     17 // along with GAS; see the file COPYING.  If not, write to the Free
     18 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
     19 // 02110-1301, USA.
     20 
     21 // Make %st first as we test for it.
     22 st, FloatReg|FloatAcc, 0, 0, 11, 33
     23 // 8 bit regs
     24 al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
     25 cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
     26 dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
     27 bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
     28 ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
     29 ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
     30 dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
     31 bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
     32 axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
     33 cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
     34 dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
     35 bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
     36 spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
     37 bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
     38 sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
     39 dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
     40 r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
     41 r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
     42 r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
     43 r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
     44 r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
     45 r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
     46 r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
     47 r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
     48 // 16 bit regs
     49 ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
     50 cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
     51 dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
     52 bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
     53 sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
     54 bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
     55 si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
     56 di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
     57 r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
     58 r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
     59 r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
     60 r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
     61 r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
     62 r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
     63 r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
     64 r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
     65 // 32 bit regs
     66 eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
     67 ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
     68 edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
     69 ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
     70 esp, Reg32, 0, 4, 4, Dw2Inval
     71 ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
     72 esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
     73 edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
     74 r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
     75 r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
     76 r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
     77 r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
     78 r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
     79 r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
     80 r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
     81 r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
     82 rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
     83 rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
     84 rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
     85 rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
     86 rsp, Reg64, 0, 4, Dw2Inval, 7
     87 rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
     88 rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
     89 rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
     90 r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
     91 r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
     92 r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
     93 r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
     94 r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
     95 r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
     96 r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
     97 r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
     98 // Vector mask registers.
     99 k0, RegMask, 0, 0, 93, 118
    100 k1, RegMask, 0, 1, 94, 119
    101 k2, RegMask, 0, 2, 95, 120
    102 k3, RegMask, 0, 3, 96, 121
    103 k4, RegMask, 0, 4, 97, 122
    104 k5, RegMask, 0, 5, 98, 123
    105 k6, RegMask, 0, 6, 99, 124
    106 k7, RegMask, 0, 7, 100, 125
    107 // Segment registers.
    108 es, SReg2, 0, 0, 40, 50
    109 cs, SReg2, 0, 1, 41, 51
    110 ss, SReg2, 0, 2, 42, 52
    111 ds, SReg2, 0, 3, 43, 53
    112 fs, SReg3, 0, 4, 44, 54
    113 gs, SReg3, 0, 5, 45, 55
    114 flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
    115 // Control registers.
    116 cr0, Control, 0, 0, Dw2Inval, Dw2Inval
    117 cr1, Control, 0, 1, Dw2Inval, Dw2Inval
    118 cr2, Control, 0, 2, Dw2Inval, Dw2Inval
    119 cr3, Control, 0, 3, Dw2Inval, Dw2Inval
    120 cr4, Control, 0, 4, Dw2Inval, Dw2Inval
    121 cr5, Control, 0, 5, Dw2Inval, Dw2Inval
    122 cr6, Control, 0, 6, Dw2Inval, Dw2Inval
    123 cr7, Control, 0, 7, Dw2Inval, Dw2Inval
    124 cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
    125 cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
    126 cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
    127 cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
    128 cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
    129 cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
    130 cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
    131 cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
    132 // Debug registers.
    133 db0, Debug, 0, 0, Dw2Inval, Dw2Inval
    134 db1, Debug, 0, 1, Dw2Inval, Dw2Inval
    135 db2, Debug, 0, 2, Dw2Inval, Dw2Inval
    136 db3, Debug, 0, 3, Dw2Inval, Dw2Inval
    137 db4, Debug, 0, 4, Dw2Inval, Dw2Inval
    138 db5, Debug, 0, 5, Dw2Inval, Dw2Inval
    139 db6, Debug, 0, 6, Dw2Inval, Dw2Inval
    140 db7, Debug, 0, 7, Dw2Inval, Dw2Inval
    141 db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
    142 db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
    143 db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
    144 db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
    145 db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
    146 db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
    147 db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
    148 db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
    149 dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
    150 dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
    151 dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
    152 dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
    153 dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
    154 dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
    155 dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
    156 dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
    157 dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
    158 dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
    159 dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
    160 dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
    161 dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
    162 dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
    163 dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
    164 dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
    165 // Test registers.
    166 tr0, Test, 0, 0, Dw2Inval, Dw2Inval
    167 tr1, Test, 0, 1, Dw2Inval, Dw2Inval
    168 tr2, Test, 0, 2, Dw2Inval, Dw2Inval
    169 tr3, Test, 0, 3, Dw2Inval, Dw2Inval
    170 tr4, Test, 0, 4, Dw2Inval, Dw2Inval
    171 tr5, Test, 0, 5, Dw2Inval, Dw2Inval
    172 tr6, Test, 0, 6, Dw2Inval, Dw2Inval
    173 tr7, Test, 0, 7, Dw2Inval, Dw2Inval
    174 // MMX and simd registers.
    175 mm0, RegMMX, 0, 0, 29, 41
    176 mm1, RegMMX, 0, 1, 30, 42
    177 mm2, RegMMX, 0, 2, 31, 43
    178 mm3, RegMMX, 0, 3, 32, 44
    179 mm4, RegMMX, 0, 4, 33, 45
    180 mm5, RegMMX, 0, 5, 34, 46
    181 mm6, RegMMX, 0, 6, 35, 47
    182 mm7, RegMMX, 0, 7, 36, 48
    183 xmm0, RegXMM, 0, 0, 21, 17
    184 xmm1, RegXMM, 0, 1, 22, 18
    185 xmm2, RegXMM, 0, 2, 23, 19
    186 xmm3, RegXMM, 0, 3, 24, 20
    187 xmm4, RegXMM, 0, 4, 25, 21
    188 xmm5, RegXMM, 0, 5, 26, 22
    189 xmm6, RegXMM, 0, 6, 27, 23
    190 xmm7, RegXMM, 0, 7, 28, 24
    191 xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
    192 xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
    193 xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
    194 xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
    195 xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
    196 xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
    197 xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
    198 xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
    199 xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
    200 xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
    201 xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
    202 xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
    203 xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
    204 xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
    205 xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
    206 xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
    207 xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
    208 xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
    209 xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
    210 xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
    211 xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
    212 xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
    213 xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
    214 xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
    215 // AVX registers.
    216 ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
    217 ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
    218 ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
    219 ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
    220 ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
    221 ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
    222 ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
    223 ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
    224 ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
    225 ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
    226 ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
    227 ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
    228 ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
    229 ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
    230 ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
    231 ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
    232 ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval
    233 ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval
    234 ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval
    235 ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval
    236 ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval
    237 ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval
    238 ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval
    239 ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval
    240 ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
    241 ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
    242 ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
    243 ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
    244 ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
    245 ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
    246 ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
    247 ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
    248 // AVX512 registers.
    249 zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval
    250 zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval
    251 zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval
    252 zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval
    253 zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval
    254 zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval
    255 zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval
    256 zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval
    257 zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval
    258 zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval
    259 zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval
    260 zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval
    261 zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval
    262 zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval
    263 zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval
    264 zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval
    265 zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval
    266 zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval
    267 zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval
    268 zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval
    269 zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval
    270 zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval
    271 zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval
    272 zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval
    273 zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
    274 zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
    275 zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
    276 zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
    277 zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
    278 zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
    279 zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
    280 zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
    281 // Bound registers for MPX
    282 bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
    283 bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
    284 bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
    285 bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
    286 // No type will make these registers rejected for all purposes except
    287 // for addressing.  This saves creating one extra type for RIP/EIP.
    288 rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
    289 eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
    290 // No type will make these registers rejected for all purposes except
    291 // for addressing.
    292 riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
    293 eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
    294 // fp regs.
    295 st(0), FloatReg|FloatAcc, 0, 0, 11, 33
    296 st(1), FloatReg, 0, 1, 12, 34
    297 st(2), FloatReg, 0, 2, 13, 35
    298 st(3), FloatReg, 0, 3, 14, 36
    299 st(4), FloatReg, 0, 4, 15, 37
    300 st(5), FloatReg, 0, 5, 16, 38
    301 st(6), FloatReg, 0, 6, 17, 39
    302 st(7), FloatReg, 0, 7, 18, 40
    303 // Pseudo-register names only used in .cfi_* directives
    304 eflags, 0, 0, 0, 9, 49
    305 rflags, 0, 0, 0, Dw2Inval, 49
    306 fs.base, 0, 0, 0, Dw2Inval, 58
    307 gs.base, 0, 0, 0, Dw2Inval, 59
    308 tr, 0, 0, 0, 48, 62
    309 ldtr, 0, 0, 0, 49, 63
    310 // st0...7 for backward compatibility
    311 st0, 0, 0, 0, 11, 33
    312 st1, 0, 0, 1, 12, 34
    313 st2, 0, 0, 2, 13, 35
    314 st3, 0, 0, 3, 14, 36
    315 st4, 0, 0, 4, 15, 37
    316 st5, 0, 0, 5, 16, 38
    317 st6, 0, 0, 6, 17, 39
    318 st7, 0, 0, 7, 18, 40
    319 fcw, 0, 0, 0, 37, 65
    320 fsw, 0, 0, 0, 38, 66
    321 mxcsr, 0, 0, 0, 39, 64
    322