Lines Matching defs:PVT
8656 MVT PVT = getPointerTy(MF->getDataLayout());
8657 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8700 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8701 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8702 const int64_t BPOffset = 4 * PVT.getStoreSize();
8705 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8794 MVT PVT = getPointerTy(MF->getDataLayout());
8795 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8799 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8802 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8803 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8805 (PVT == MVT::i64)
8812 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8813 const int64_t SPOffset = 2 * PVT.getStoreSize();
8814 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8815 const int64_t BPOffset = 4 * PVT.getStoreSize();
8822 if (PVT == MVT::i64) {
8834 if (PVT == MVT::i64) {
8846 if (PVT == MVT::i64) {
8858 if (PVT == MVT::i64) {
8870 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8881 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8882 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
