Lines Matching defs:BrCond
131 /// BrCond - Conditions for end of block conditional branches.
150 SmallVector<MachineOperand, 4> BrCond;
522 if (!TII->reverseBranchCondition(BBI.BrCond)) {
524 TII->insertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
582 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
789 if (TrueBBI.BrCond.size() == 0 ||
790 FalseBBI.BrCond.size() == 0)
913 BBI.BrCond.clear();
915 !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
916 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
921 if (BBI.BrCond.size()) {
1068 if (!hasCommonTail && BBI.BrCond.size()) {
1074 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1123 if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
1164 RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1184 bool TrueFeasible = FeasibilityAnalysis(TrueBBI, BBI.BrCond,
1233 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
1249 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
1258 FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
1422 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1508 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1587 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
1588 CvtBBI->BrCond.end());
1679 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1682 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
1898 TrueBBI.BrCond, dl);
