Lines Matching refs:im
30 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
35 im->sysconf.ddrlaw[0].ar =
37 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
42 im->ddr.csbnds[0].csbnds =
46 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
49 im->ddr.cs_config[1] = 0;
50 im->ddr.cs_config[2] = 0;
51 im->ddr.cs_config[3] = 0;
53 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
54 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
56 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
57 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
59 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
60 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
61 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
62 im->ddr.sdram_mode =
64 im->ddr.sdram_interval =
67 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
71 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
73 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
74 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
75 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
76 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
77 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
122 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
125 volatile ddr83xx_t *ddr = &im->ddr;
128 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
132 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
