Lines Matching refs:ddr
16 * regs has the to-be-set values for DDR controller registers
17 * ctrl_num is the DDR controller number
21 * Dividing the initialization to two steps to deassert DDR reset signal
28 struct ccsr_ddr __iomem *ddr;
44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
58 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
70 out_be32(&ddr->eor, regs->ddr_eor);
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
94 out_be32(&ddr->cs0_config, regs->cs[i].config);
95 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
98 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
99 out_be32(&ddr->cs1_config, regs->cs[i].config);
100 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
103 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
104 out_be32(&ddr->cs2_config, regs->cs[i].config);
105 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
108 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
109 out_be32(&ddr->cs3_config, regs->cs[i].config);
110 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
114 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
115 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
116 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
117 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
118 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
119 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
120 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
121 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
122 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
123 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
124 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
125 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
126 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
127 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
128 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
129 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
130 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
131 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
132 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
133 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
141 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
143 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
146 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
147 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
148 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
149 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
152 out_be32(&ddr->sdram_cfg_2,
154 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
155 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
158 out_be32(&ddr->ddr_cdr2,
163 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
164 out_be32(&ddr->init_addr, regs->ddr_init_addr);
165 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
166 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
168 out_be32(&ddr->err_disable, regs->err_disable);
169 out_be32(&ddr->err_int_en, regs->err_int_en);
173 out_be32(&ddr->debug[i], regs->debug[i]);
178 out_be32(&ddr->debug[12], 0x00000015);
179 out_be32(&ddr->debug[21], 0x24000000);
185 * control register is set. Because all DDR components are connected to
199 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
203 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
204 out_be32(&ddr->debug[2], 0x00000400);
205 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
206 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
207 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
208 out_be32(&ddr->mtcr, 0);
209 save1 = in_be32(&ddr->debug[12]);
210 save2 = in_be32(&ddr->debug[21]);
211 out_be32(&ddr->debug[12], 0x00000015);
212 out_be32(&ddr->debug[21], 0x24000000);
213 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
214 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
217 while (!(in_be32(&ddr->debug[1]) & 0x2))
222 out_be32(&ddr->sdram_md_cntl,
231 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
233 out_be32(&ddr->sdram_md_cntl,
242 out_be32(&ddr->sdram_md_cntl,
251 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
253 out_be32(&ddr->sdram_md_cntl,
262 out_be32(&ddr->sdram_md_cntl,
271 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
273 out_be32(&ddr->sdram_md_cntl,
282 out_be32(&ddr->sdram_md_cntl,
291 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
293 out_be32(&ddr->sdram_md_cntl,
302 out_be32(&ddr->sdram_md_cntl,
311 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
313 out_be32(&ddr->sdram_md_cntl,
324 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
327 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
328 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
329 out_be32(&ddr->debug[2], 0x0);
330 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
331 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
332 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
333 out_be32(&ddr->debug[12], save1);
334 out_be32(&ddr->debug[21], save2);
335 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
340 * For 8572 DDR1 erratum - DDR controller may enter illegal state
346 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
347 && in_be32(&ddr->sdram_cfg) & 0x80000) {
349 setbits_be32(&ddr->debug[0], 1);
364 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
366 in_be32(&ddr->sdram_cfg_2));
369 setbits_be32(&ddr->debug[2], 0x400);
370 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
376 * the DDR clock setup and the DDR config enable.
386 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
389 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
392 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
395 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
420 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
432 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
445 clrbits_be32(&ddr->debug[2], 0x400);
446 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
450 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
452 in_be32(&ddr->sdram_cfg_2));
455 setbits_be32(&ddr->debug[0], 0x10000);
456 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
459 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
461 in_be32(&ddr->timing_cfg_2));
464 out_be32(&ddr->debug[5], 0x9f9f9f9f);
465 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
468 out_be32(&ddr->debug[6], 0x9f9f9f9f);
469 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
472 setbits_be32(&ddr->debug[1], 0x800);
473 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
476 while (in_be32(&ddr->debug[1]) & 0x800)
480 clrbits_be32(&ddr->debug[0], 0x10000);
481 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
484 setbits_be32(&ddr->sdram_cfg_2,
486 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
490 setbits_be32(&ddr->debug[1], 0x400);
491 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
494 while (in_be32(&ddr->debug[1]) & 0x400)
502 setbits_be32(&ddr->sdram_cfg_2,
504 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
509 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
527 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
530 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
533 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
537 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
540 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
544 clrbits_be32(&ddr->sdram_cfg, 0x2);
550 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
