1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2008-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <fsl_ddr_sdram.h> 9 #include <asm/processor.h> 10 11 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 12 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 13 #endif 14 15 /* 16 * regs has the to-be-set values for DDR controller registers 17 * ctrl_num is the DDR controller number 18 * step: 0 goes through the initialization in one pass 19 * 1 sets registers and returns before enabling controller 20 * 2 resumes from step 1 and continues to initialize 21 * Dividing the initialization to two steps to deassert DDR reset signal 22 * to comply with JEDEC specs for RDIMMs. 23 */ 24 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 25 unsigned int ctrl_num, int step) 26 { 27 unsigned int i, bus_width; 28 struct ccsr_ddr __iomem *ddr; 29 u32 temp_sdram_cfg; 30 u32 total_gb_size_per_controller; 31 int timeout; 32 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 33 int timeout_save; 34 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; 35 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; 36 int csn = -1; 37 #endif 38 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 39 u32 save1, save2; 40 #endif 41 42 switch (ctrl_num) { 43 case 0: 44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 45 break; 46 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 47 case 1: 48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 49 break; 50 #endif 51 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 52 case 2: 53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 54 break; 55 #endif 56 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 57 case 3: 58 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 59 break; 60 #endif 61 default: 62 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 63 return; 64 } 65 66 if (step == 2) 67 goto step2; 68 69 if (regs->ddr_eor) 70 out_be32(&ddr->eor, regs->ddr_eor); 71 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 72 debug("Workaround for ERRATUM_DDR111_DDR134\n"); 73 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 74 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; 75 cs_ea = regs->cs[i].bnds & 0xfff; 76 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { 77 csn = i; 78 csn_bnds_backup = regs->cs[i].bnds; 79 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; 80 if (cs_ea > 0xeff) 81 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; 82 else 83 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; 84 debug("Found cs%d_bns (0x%08x) covering 0xff000000, " 85 "change it to 0x%x\n", 86 csn, csn_bnds_backup, regs->cs[i].bnds); 87 break; 88 } 89 } 90 #endif 91 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 92 if (i == 0) { 93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 94 out_be32(&ddr->cs0_config, regs->cs[i].config); 95 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); 96 97 } else if (i == 1) { 98 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 99 out_be32(&ddr->cs1_config, regs->cs[i].config); 100 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); 101 102 } else if (i == 2) { 103 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 104 out_be32(&ddr->cs2_config, regs->cs[i].config); 105 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); 106 107 } else if (i == 3) { 108 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 109 out_be32(&ddr->cs3_config, regs->cs[i].config); 110 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); 111 } 112 } 113 114 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); 115 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); 116 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); 117 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 118 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); 119 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 120 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 121 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 122 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 123 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 124 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 125 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 126 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 127 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 128 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); 129 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 130 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); 131 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); 132 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 133 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 134 #ifndef CONFIG_SYS_FSL_DDR_EMU 135 /* 136 * Skip these two registers if running on emulator 137 * because emulator doesn't have skew between bytes. 138 */ 139 140 if (regs->ddr_wrlvl_cntl_2) 141 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 142 if (regs->ddr_wrlvl_cntl_3) 143 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 144 #endif 145 146 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 147 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 148 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 149 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); 150 #ifdef CONFIG_DEEP_SLEEP 151 if (is_warm_boot()) { 152 out_be32(&ddr->sdram_cfg_2, 153 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 154 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 155 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 156 157 /* DRAM VRef will not be trained */ 158 out_be32(&ddr->ddr_cdr2, 159 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 160 } else 161 #endif 162 { 163 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 164 out_be32(&ddr->init_addr, regs->ddr_init_addr); 165 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 166 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); 167 } 168 out_be32(&ddr->err_disable, regs->err_disable); 169 out_be32(&ddr->err_int_en, regs->err_int_en); 170 for (i = 0; i < 32; i++) { 171 if (regs->debug[i]) { 172 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); 173 out_be32(&ddr->debug[i], regs->debug[i]); 174 } 175 } 176 177 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 178 out_be32(&ddr->debug[12], 0x00000015); 179 out_be32(&ddr->debug[21], 0x24000000); 180 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ 181 182 /* 183 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 184 * deasserted. Clocks start when any chip select is enabled and clock 185 * control register is set. Because all DDR components are connected to 186 * one reset signal, this needs to be done in two steps. Step 1 is to 187 * get the clocks started. Step 2 resumes after reset signal is 188 * deasserted. 189 */ 190 if (step == 1) { 191 udelay(200); 192 return; 193 } 194 195 step2: 196 /* Set, but do not enable the memory */ 197 temp_sdram_cfg = regs->ddr_sdram_cfg; 198 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 199 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); 200 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 201 debug("Workaround for ERRATUM_DDR_A003\n"); 202 if (regs->ddr_sdram_rcw_2 & 0x00f00000) { 203 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); 204 out_be32(&ddr->debug[2], 0x00000400); 205 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); 206 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); 207 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); 208 out_be32(&ddr->mtcr, 0); 209 save1 = in_be32(&ddr->debug[12]); 210 save2 = in_be32(&ddr->debug[21]); 211 out_be32(&ddr->debug[12], 0x00000015); 212 out_be32(&ddr->debug[21], 0x24000000); 213 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); 214 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); 215 216 asm volatile("sync;isync"); 217 while (!(in_be32(&ddr->debug[1]) & 0x2)) 218 ; 219 220 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { 221 case 0x00000000: 222 out_be32(&ddr->sdram_md_cntl, 223 MD_CNTL_MD_EN | 224 MD_CNTL_CS_SEL_CS0_CS1 | 225 0x04000000 | 226 MD_CNTL_WRCW | 227 MD_CNTL_MD_VALUE(0x02)); 228 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 229 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 230 break; 231 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 232 ; 233 out_be32(&ddr->sdram_md_cntl, 234 MD_CNTL_MD_EN | 235 MD_CNTL_CS_SEL_CS2_CS3 | 236 0x04000000 | 237 MD_CNTL_WRCW | 238 MD_CNTL_MD_VALUE(0x02)); 239 #endif 240 break; 241 case 0x00100000: 242 out_be32(&ddr->sdram_md_cntl, 243 MD_CNTL_MD_EN | 244 MD_CNTL_CS_SEL_CS0_CS1 | 245 0x04000000 | 246 MD_CNTL_WRCW | 247 MD_CNTL_MD_VALUE(0x0a)); 248 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 249 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 250 break; 251 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 252 ; 253 out_be32(&ddr->sdram_md_cntl, 254 MD_CNTL_MD_EN | 255 MD_CNTL_CS_SEL_CS2_CS3 | 256 0x04000000 | 257 MD_CNTL_WRCW | 258 MD_CNTL_MD_VALUE(0x0a)); 259 #endif 260 break; 261 case 0x00200000: 262 out_be32(&ddr->sdram_md_cntl, 263 MD_CNTL_MD_EN | 264 MD_CNTL_CS_SEL_CS0_CS1 | 265 0x04000000 | 266 MD_CNTL_WRCW | 267 MD_CNTL_MD_VALUE(0x12)); 268 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 269 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 270 break; 271 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 272 ; 273 out_be32(&ddr->sdram_md_cntl, 274 MD_CNTL_MD_EN | 275 MD_CNTL_CS_SEL_CS2_CS3 | 276 0x04000000 | 277 MD_CNTL_WRCW | 278 MD_CNTL_MD_VALUE(0x12)); 279 #endif 280 break; 281 case 0x00300000: 282 out_be32(&ddr->sdram_md_cntl, 283 MD_CNTL_MD_EN | 284 MD_CNTL_CS_SEL_CS0_CS1 | 285 0x04000000 | 286 MD_CNTL_WRCW | 287 MD_CNTL_MD_VALUE(0x1a)); 288 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 289 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 290 break; 291 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 292 ; 293 out_be32(&ddr->sdram_md_cntl, 294 MD_CNTL_MD_EN | 295 MD_CNTL_CS_SEL_CS2_CS3 | 296 0x04000000 | 297 MD_CNTL_WRCW | 298 MD_CNTL_MD_VALUE(0x1a)); 299 #endif 300 break; 301 default: 302 out_be32(&ddr->sdram_md_cntl, 303 MD_CNTL_MD_EN | 304 MD_CNTL_CS_SEL_CS0_CS1 | 305 0x04000000 | 306 MD_CNTL_WRCW | 307 MD_CNTL_MD_VALUE(0x02)); 308 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 309 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) 310 break; 311 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) 312 ; 313 out_be32(&ddr->sdram_md_cntl, 314 MD_CNTL_MD_EN | 315 MD_CNTL_CS_SEL_CS2_CS3 | 316 0x04000000 | 317 MD_CNTL_WRCW | 318 MD_CNTL_MD_VALUE(0x02)); 319 #endif 320 printf("Unsupported RC10\n"); 321 break; 322 } 323 324 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) 325 ; 326 udelay(6); 327 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); 328 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); 329 out_be32(&ddr->debug[2], 0x0); 330 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 331 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 332 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 333 out_be32(&ddr->debug[12], save1); 334 out_be32(&ddr->debug[21], save2); 335 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); 336 337 } 338 #endif 339 /* 340 * For 8572 DDR1 erratum - DDR controller may enter illegal state 341 * when operatiing in 32-bit bus mode with 4-beat bursts, 342 * This erratum does not affect DDR3 mode, only for DDR2 mode. 343 */ 344 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 345 debug("Workaround for ERRATUM_DDR_115\n"); 346 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) 347 && in_be32(&ddr->sdram_cfg) & 0x80000) { 348 /* set DEBUG_1[31] */ 349 setbits_be32(&ddr->debug[0], 1); 350 } 351 #endif 352 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 353 debug("Workaround for ERRATUM_DDR111_DDR134\n"); 354 /* 355 * This is the combined workaround for DDR111 and DDR134 356 * following the published errata for MPC8572 357 */ 358 359 /* 1. Set EEBACR[3] */ 360 setbits_be32(&ecm->eebacr, 0x10000000); 361 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); 362 363 /* 2. Set DINIT in SDRAM_CFG_2*/ 364 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); 365 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", 366 in_be32(&ddr->sdram_cfg_2)); 367 368 /* 3. Set DEBUG_3[21] */ 369 setbits_be32(&ddr->debug[2], 0x400); 370 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); 371 372 #endif /* part 1 of the workaound */ 373 374 /* 375 * 500 painful micro-seconds must elapse between 376 * the DDR clock setup and the DDR config enable. 377 * DDR2 need 200 us, and DDR3 need 500 us from spec, 378 * we choose the max, that is 500 us for all of case. 379 */ 380 udelay(500); 381 asm volatile("sync;isync"); 382 383 #ifdef CONFIG_DEEP_SLEEP 384 if (is_warm_boot()) { 385 /* enter self-refresh */ 386 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); 387 /* do board specific memory setup */ 388 board_mem_sleep_setup(); 389 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 390 } else 391 #endif 392 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); 393 394 /* Let the controller go */ 395 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 396 asm volatile("sync;isync"); 397 398 total_gb_size_per_controller = 0; 399 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 400 if (!(regs->cs[i].config & 0x80000000)) 401 continue; 402 total_gb_size_per_controller += 1 << ( 403 ((regs->cs[i].config >> 14) & 0x3) + 2 + 404 ((regs->cs[i].config >> 8) & 0x7) + 12 + 405 ((regs->cs[i].config >> 0) & 0x7) + 8 + 406 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 407 26); /* minus 26 (count of 64M) */ 408 } 409 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ 410 total_gb_size_per_controller *= 3; 411 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ 412 total_gb_size_per_controller <<= 1; 413 /* 414 * total memory / bus width = transactions needed 415 * transactions needed / data rate = seconds 416 * to add plenty of buffer, double the time 417 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 418 * Let's wait for 800ms 419 */ 420 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) 421 >> SDRAM_CFG_DBW_SHIFT); 422 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 423 (get_ddr_freq(ctrl_num) >> 20)) << 1; 424 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 425 timeout_save = timeout; 426 #endif 427 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 428 debug("total %d GB\n", total_gb_size_per_controller); 429 debug("Need to wait up to %d * 10ms\n", timeout); 430 431 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 432 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 433 (timeout >= 0)) { 434 udelay(10000); /* throttle polling rate */ 435 timeout--; 436 } 437 438 if (timeout <= 0) 439 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 440 441 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 442 /* continue this workaround */ 443 444 /* 4. Clear DEBUG3[21] */ 445 clrbits_be32(&ddr->debug[2], 0x400); 446 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); 447 448 /* DDR134 workaround starts */ 449 /* A: Clear sdram_cfg_2[odt_cfg] */ 450 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); 451 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", 452 in_be32(&ddr->sdram_cfg_2)); 453 454 /* B: Set DEBUG1[15] */ 455 setbits_be32(&ddr->debug[0], 0x10000); 456 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); 457 458 /* C: Set timing_cfg_2[cpo] to 0b11111 */ 459 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); 460 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", 461 in_be32(&ddr->timing_cfg_2)); 462 463 /* D: Set D6 to 0x9f9f9f9f */ 464 out_be32(&ddr->debug[5], 0x9f9f9f9f); 465 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); 466 467 /* E: Set D7 to 0x9f9f9f9f */ 468 out_be32(&ddr->debug[6], 0x9f9f9f9f); 469 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); 470 471 /* F: Set D2[20] */ 472 setbits_be32(&ddr->debug[1], 0x800); 473 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); 474 475 /* G: Poll on D2[20] until cleared */ 476 while (in_be32(&ddr->debug[1]) & 0x800) 477 udelay(10000); /* throttle polling rate */ 478 479 /* H: Clear D1[15] */ 480 clrbits_be32(&ddr->debug[0], 0x10000); 481 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); 482 483 /* I: Set sdram_cfg_2[odt_cfg] */ 484 setbits_be32(&ddr->sdram_cfg_2, 485 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); 486 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); 487 488 /* Continuing with the DDR111 workaround */ 489 /* 5. Set D2[21] */ 490 setbits_be32(&ddr->debug[1], 0x400); 491 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); 492 493 /* 6. Poll D2[21] until its cleared */ 494 while (in_be32(&ddr->debug[1]) & 0x400) 495 udelay(10000); /* throttle polling rate */ 496 497 /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ 498 debug("Wait for %d * 10ms\n", timeout_save); 499 udelay(timeout_save * 10000); 500 501 /* 8. Set sdram_cfg_2[dinit] if options requires */ 502 setbits_be32(&ddr->sdram_cfg_2, 503 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); 504 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); 505 506 /* 9. Poll until dinit is cleared */ 507 timeout = timeout_save; 508 debug("Need to wait up to %d * 10ms\n", timeout); 509 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 510 (timeout >= 0)) { 511 udelay(10000); /* throttle polling rate */ 512 timeout--; 513 } 514 515 if (timeout <= 0) 516 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 517 518 /* 10. Clear EEBACR[3] */ 519 clrbits_be32(&ecm->eebacr, 10000000); 520 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); 521 522 if (csn != -1) { 523 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; 524 *csn_bnds_t = csn_bnds_backup; 525 debug("Change cs%d_bnds back to 0x%08x\n", 526 csn, regs->cs[csn].bnds); 527 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ 528 switch (csn) { 529 case 0: 530 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); 531 break; 532 case 1: 533 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); 534 break; 535 #if CONFIG_CHIP_SELECTS_PER_CTRL > 2 536 case 2: 537 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); 538 break; 539 case 3: 540 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); 541 break; 542 #endif 543 } 544 clrbits_be32(&ddr->sdram_cfg, 0x2); 545 } 546 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ 547 #ifdef CONFIG_DEEP_SLEEP 548 if (is_warm_boot()) 549 /* exit self-refresh */ 550 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); 551 #endif 552 } 553
