| /external/u-boot/board/sbc8548/ |
| ddr.c | 59 * existed on earlier boards; the workaround moved the DDR
79 printf("DDR: failed to read SPD from addr %u\n", i2c_address);
91 struct ccsr_ddr __iomem *ddr = local
94 out_be32(&ddr->cs0_bnds, 0x0000007f);
95 out_be32(&ddr->cs1_bnds, 0x008000ff);
96 out_be32(&ddr->cs2_bnds, 0x00000000);
97 out_be32(&ddr->cs3_bnds, 0x00000000);
99 out_be32(&ddr->cs0_config, 0x80010101);
100 out_be32(&ddr->cs1_config, 0x80010101);
101 out_be32(&ddr->cs2_config, 0x00000000)
[all...] |
| /external/u-boot/board/sbc8641d/ |
| sbc8641d.c | 51 debug (" DDR: ");
99 volatile struct ccsr_ddr *ddr = &immap->im_ddr1; local
101 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
102 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
103 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
104 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
105 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
106 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
107 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
108 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG
[all...] |
| /external/u-boot/board/freescale/bsc9131rdb/ |
| spl_minimal.c | 22 struct ccsr_ddr __iomem *ddr = local
25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
28 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
29 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
31 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2)
[all...] |
| /external/u-boot/post/cpu/mpc83xx/ |
| ecc.c | 23 static inline void ecc_clear(ddr83xx_t *ddr)
26 __raw_writel(0, &ddr->capture_address);
27 __raw_writel(0, &ddr->capture_data_hi);
28 __raw_writel(0, &ddr->capture_data_lo);
29 __raw_writel(0, &ddr->capture_ecc);
30 __raw_writel(0, &ddr->capture_attributes);
33 out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);
36 out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\
50 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; local
[all...] |
| /external/u-boot/drivers/ddr/fsl/ |
| arm_ddr_gen3.c | 22 * regs has the to-be-set values for DDR controller registers
23 * ctrl_num is the DDR controller number
27 * Dividing the initialization to two steps to deassert DDR reset signal
34 struct ccsr_ddr __iomem *ddr; local
41 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
45 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
50 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
55 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
67 ddr_out32(&ddr->eor, regs->ddr_eor);
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds)
[all...] |
| fsl_ddr_gen4.c | 42 * regs has the to-be-set values for DDR controller registers
43 * ctrl_num is the DDR controller number
47 * Dividing the initialization to two steps to deassert DDR reset signal
54 struct ccsr_ddr __iomem *ddr; local
75 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
79 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
84 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
89 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
102 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
105 ddr_out32(&ddr->eor, regs->ddr_eor)
[all...] |
| mpc86xx_ddr.c | 18 struct ccsr_ddr __iomem *ddr; local
22 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
25 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
35 out_be32(&ddr->cs0_config, regs->cs[i].config);
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
39 out_be32(&ddr->cs1_config, regs->cs[i].config);
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs2_config, regs->cs[i].config);
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds)
[all...] |
| mpc85xx_ddr_gen1.c | 18 struct ccsr_ddr __iomem *ddr = local
28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
29 out_be32(&ddr->cs0_config, regs->cs[i].config);
32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
33 out_be32(&ddr->cs1_config, regs->cs[i].config);
36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
37 out_be32(&ddr->cs2_config, regs->cs[i].config);
40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
41 out_be32(&ddr->cs3_config, regs->cs[i].config);
45 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1)
74 struct ccsr_ddr __iomem *ddr = local
[all...] |
| mpc85xx_ddr_gen3.c | 16 * regs has the to-be-set values for DDR controller registers
17 * ctrl_num is the DDR controller number
21 * Dividing the initialization to two steps to deassert DDR reset signal
28 struct ccsr_ddr __iomem *ddr; local
44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
58 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
70 out_be32(&ddr->eor, regs->ddr_eor);
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds)
[all...] |
| mpc85xx_ddr_gen2.c | 19 struct ccsr_ddr __iomem *ddr = local
34 * Set the DDR IO receiver to an acceptable bias point.
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
50 out_be32(&ddr->cs0_config, regs->cs[i].config);
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
54 out_be32(&ddr->cs1_config, regs->cs[i].config);
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
58 out_be32(&ddr->cs2_config, regs->cs[i].config);
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
62 out_be32(&ddr->cs3_config, regs->cs[i].config)
[all...] |
| ctrl_regs.c | 8 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
225 ddr->cs[i].config = (0
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
289 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
291 * Avoid writing for DDR I. The new PQ38 DDR controlle
2658 struct ccsr_ddr __iomem *ddr = local
[all...] |
| /external/u-boot/arch/powerpc/cpu/mpc83xx/ |
| ecc.c | 18 struct ccsr_ddr __iomem *ddr = &immap->ddr; local
20 ddr83xx_t *ddr = &immap->ddr; local
24 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
29 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
31 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
33 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
38 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
40 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0)
102 struct ccsr_ddr __iomem *ddr = &immap->ddr; local
104 ddr83xx_t *ddr = &immap->ddr; local
[all...] |
| /external/u-boot/board/freescale/bsc9132qds/ |
| spl_minimal.c | 19 struct ccsr_ddr __iomem *ddr = local
22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2)
[all...] |
| /external/u-boot/board/socrates/ |
| sdram.c | 18 * Autodetect onboard DDR SDRAM on 85xx platforms
26 struct ccsr_ddr __iomem *ddr = local
32 ddr->cs0_config = 0;
33 ddr->sdram_cfg = 0;
35 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
36 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
37 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
38 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
39 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
40 ddr->sdram_mode = CONFIG_SYS_DDR_MODE
[all...] |
| /external/u-boot/board/freescale/ls2080a/ |
| Makefile | 6 obj-y += ddr.o
|
| /external/u-boot/board/freescale/ls2080ardb/ |
| Makefile | 6 obj-y += ddr.o
|
| /external/u-boot/board/freescale/mpc8315erdb/ |
| sdram.c | 57 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
58 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
61 im->ddr.cs_config[1] = 0;
63 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
64 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
65 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
66 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
67 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
70 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
72 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG
[all...] |
| /external/u-boot/board/freescale/mpc8308rdb/ |
| sdram.c | 40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
44 out_be32(&im->ddr.cs_config[1], 0);
46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
52 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
53 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2)
[all...] |
| /external/u-boot/board/gdsys/mpc8308/ |
| sdram.c | 41 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
42 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
45 out_be32(&im->ddr.cs_config[1], 0);
47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
48 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
50 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
51 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
53 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
54 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2)
[all...] |
| /external/u-boot/board/mpc8308_p1m/ |
| sdram.c | 36 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
37 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
40 out_be32(&im->ddr.cs_config[1], 0);
42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
43 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
46 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
48 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
49 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2)
[all...] |
| /external/u-boot/board/freescale/ls1021aiot/ |
| ls1021aiot.c | 49 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; local
52 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
54 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
55 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
57 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
58 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
59 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
60 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
61 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
62 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5)
[all...] |
| /external/u-boot/board/freescale/mpc8313erdb/ |
| sdram.c | 63 im->ddr.csbnds[0].csbnds =
67 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
70 im->ddr.cs_config[1] = 0;
72 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
73 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
76 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
80 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
83 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG
[all...] |
| /external/u-boot/arch/mips/mach-ath79/ar933x/ |
| Makefile | 4 obj-y += ddr.o
|
| /external/u-boot/arch/mips/mach-ath79/ar934x/ |
| Makefile | 5 obj-y += ddr.o
|
| /external/u-boot/arch/mips/mach-ath79/qca953x/ |
| Makefile | 4 obj-y += ddr.o
|
