1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/arch/immap_ls102xa.h> 8 #include <asm/arch/clock.h> 9 #include <asm/arch/fsl_serdes.h> 10 #include <asm/arch/ls102xa_stream_id.h> 11 12 #include <asm/arch/ls102xa_devdis.h> 13 #include <asm/arch/ls102xa_soc.h> 14 #include <asm/arch/ls102xa_sata.h> 15 #include <fsl_csu.h> 16 #include <fsl_esdhc.h> 17 #include <fsl_immap.h> 18 #include <netdev.h> 19 #include <fsl_mdio.h> 20 #include <tsec.h> 21 #include <spl.h> 22 23 #include <fsl_validate.h> 24 #include "../common/sleep.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define DDR_SIZE 0x40000000 29 30 31 int checkboard(void) 32 { 33 puts("Board: LS1021AIOT\n"); 34 35 #ifndef CONFIG_QSPI_BOOT 36 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 37 u32 cpldrev; 38 39 cpldrev = in_be32(&dcfg->gpporcr1); 40 41 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & 42 0xf)); 43 #endif 44 return 0; 45 } 46 47 void ddrmc_init(void) 48 { 49 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 50 u32 temp_sdram_cfg, tmp; 51 52 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 53 54 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 55 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 56 57 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 58 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 59 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 60 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 61 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 62 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 63 64 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 65 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 66 67 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 68 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 69 70 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 71 72 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 73 74 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 75 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 76 77 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 78 79 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 80 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 81 82 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 83 84 /* DDR erratum A-009942 */ 85 tmp = in_be32(&ddr->debug[28]); 86 out_be32(&ddr->debug[28], tmp | 0x0070006f); 87 88 udelay(500); 89 90 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 91 92 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 93 } 94 95 int dram_init(void) 96 { 97 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 98 ddrmc_init(); 99 #endif 100 101 gd->ram_size = DDR_SIZE; 102 return 0; 103 } 104 105 #ifdef CONFIG_FSL_ESDHC 106 struct fsl_esdhc_cfg esdhc_cfg[1] = { 107 {CONFIG_SYS_FSL_ESDHC_ADDR}, 108 }; 109 110 int board_mmc_init(bd_t *bis) 111 { 112 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 113 114 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 115 } 116 117 #endif 118 119 #ifdef CONFIG_TSEC_ENET 120 int board_eth_init(bd_t *bis) 121 { 122 struct fsl_pq_mdio_info mdio_info; 123 struct tsec_info_struct tsec_info[4]; 124 int num = 0; 125 126 #ifdef CONFIG_TSEC1 127 SET_STD_TSEC_INFO(tsec_info[num], 1); 128 if (is_serdes_configured(SGMII_TSEC1)) { 129 puts("eTSEC1 is in sgmii mode.\n"); 130 tsec_info[num].flags |= TSEC_SGMII; 131 } 132 num++; 133 #endif 134 #ifdef CONFIG_TSEC2 135 SET_STD_TSEC_INFO(tsec_info[num], 2); 136 if (is_serdes_configured(SGMII_TSEC2)) { 137 puts("eTSEC2 is in sgmii mode.\n"); 138 tsec_info[num].flags |= TSEC_SGMII; 139 } 140 num++; 141 #endif 142 if (!num) { 143 printf("No TSECs initialized\n"); 144 return 0; 145 } 146 147 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 148 mdio_info.name = DEFAULT_MII_NAME; 149 fsl_pq_mdio_init(bis, &mdio_info); 150 151 tsec_eth_init(bis, tsec_info, num); 152 153 return pci_eth_init(bis); 154 } 155 #endif 156 157 int board_early_init_f(void) 158 { 159 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 160 161 #ifdef CONFIG_TSEC_ENET 162 /* clear BD & FR bits for BE BD's and frame data */ 163 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 164 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 165 166 #endif 167 168 arch_soc_init(); 169 170 return 0; 171 } 172 173 #ifdef CONFIG_SPL_BUILD 174 void board_init_f(ulong dummy) 175 { 176 /* Clear the BSS */ 177 memset(__bss_start, 0, __bss_end - __bss_start); 178 179 get_clocks(); 180 181 preloader_console_init(); 182 183 dram_init(); 184 185 /* Allow OCRAM access permission as R/W */ 186 187 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 188 enable_layerscape_ns_access(); 189 #endif 190 191 board_init_r(NULL, 0); 192 } 193 #endif 194 195 int board_init(void) 196 { 197 #ifndef CONFIG_SYS_FSL_NO_SERDES 198 fsl_serdes_init(); 199 #endif 200 201 ls102xa_smmu_stream_id_init(); 202 203 return 0; 204 } 205 206 #ifdef CONFIG_BOARD_LATE_INIT 207 int board_late_init(void) 208 { 209 #ifdef CONFIG_SCSI_AHCI_PLAT 210 ls1021a_sata_init(); 211 #endif 212 213 return 0; 214 } 215 #endif 216 217 #if defined(CONFIG_MISC_INIT_R) 218 int misc_init_r(void) 219 { 220 #ifdef CONFIG_FSL_DEVICE_DISABLE 221 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 222 223 #endif 224 225 #ifdef CONFIG_FSL_CAAM 226 return sec_init(); 227 #endif 228 } 229 #endif 230 231 int ft_board_setup(void *blob, bd_t *bd) 232 { 233 ft_cpu_setup(blob, bd); 234 235 #ifdef CONFIG_PCI 236 ft_pci_setup(blob, bd); 237 #endif 238 239 return 0; 240 } 241 242 void flash_write16(u16 val, void *addr) 243 { 244 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 245 246 __raw_writew(shftval, addr); 247 } 248 249 u16 flash_read16(void *addr) 250 { 251 u16 val = __raw_readw(addr); 252 253 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 254 } 255
