Lines Matching defs:pcie
3 * Intel FPGA PCIe host controller driver
37 #define RP_CFG_ADDR(pcie, reg) \
38 ((pcie->hip_base) + (reg) + (1 << 20))
41 #define TLP_CFGRD_DW0(pcie, bus) \
42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
46 #define TLP_CFGWR_DW0(pcie, bus) \
47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
51 #define TLP_CFG_DW1(pcie, tag, be) \
52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
62 #define IS_ROOT_PORT(pcie, bdf) \
63 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
69 * struct intel_fpga_pcie - Intel FPGA PCIe controller state
73 * @first_busno: This driver supports multiple PCIe controllers.
74 * first_busno stores the bus number of the PCIe root-port
75 * number which may vary depending on the PCIe setup.
85 * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
87 * into PCIe space using these registers, so it can be reached by DMA from
90 * sizing and resource allocation by PCIe core.
92 static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie,
95 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 &&
102 static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value,
105 writel(value, pcie->cra_base + reg);
108 static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg)
110 return readl(pcie->cra_base + reg);
113 static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie)
115 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA))
119 static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie,
123 if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie))
127 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0)
130 if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0)
136 static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl)
138 cra_writel(pcie, reg0, RP_TX_REG0);
139 cra_writel(pcie, ctrl, RP_TX_CNTRL);
142 static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value)
151 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
156 dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
160 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
161 dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
179 dev_err(pcie->dev, "read TLP packet timed out\n");
183 static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers,
186 tlp_write_tx(pcie, headers[0], RP_TX_SOP);
188 tlp_write_tx(pcie, headers[1], 0);
190 tlp_write_tx(pcie, headers[2], 0);
192 tlp_write_tx(pcie, data, RP_TX_EOP);
195 static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
201 headers[0] = TLP_CFGRD_DW0(pcie, busno);
202 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
205 tlp_write_packet(pcie, headers, 0);
207 return tlp_read_packet(pcie, value);
210 static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
216 headers[0] = TLP_CFGWR_DW0(pcie, busno);
217 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
220 tlp_write_packet(pcie, headers, value);
222 return tlp_read_packet(pcie, NULL);
228 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
230 *paddress = RP_CFG_ADDR(pcie, offset);
248 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
257 pcie->first_busno = (u8)(value);
275 static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie,
284 if (IS_ROOT_PORT(pcie, bdf))
285 return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf,
289 ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK,
294 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
301 static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie,
308 dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n",
310 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
314 if (IS_ROOT_PORT(pcie, bdf))
315 return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset,
321 return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK,
329 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
331 dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n",
334 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) {
339 if (!intel_fpga_pcie_addr_valid(pcie, bdf)) {
344 return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size);
351 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
353 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset))
356 if (!intel_fpga_pcie_addr_valid(pcie, bdf))
359 return _pcie_intel_fpga_write_config(pcie, bdf, offset, value,
365 struct intel_fpga_pcie *pcie = dev_get_priv(dev);
367 pcie->bus = pci_get_controller(dev);
368 pcie->first_busno = dev->seq;
371 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
373 cra_writel(pcie, 0, P2A_INT_ENABLE);
380 struct intel_fpga_pcie *pcie = dev_get_priv(dev);
394 pcie->cra_base = map_physmem(reg_res.start,
405 pcie->hip_base = map_physmem(reg_res.start,
418 { .compatible = "altr,pcie-root-port-2.0" },
