1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel FPGA PCIe host controller driver 4 * 5 * Copyright (C) 2013-2018 Intel Corporation. All rights reserved 6 * 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <pci.h> 12 #include <asm/io.h> 13 14 #define RP_TX_REG0 0x2000 15 #define RP_TX_CNTRL 0x2004 16 #define RP_TX_SOP BIT(0) 17 #define RP_TX_EOP BIT(1) 18 #define RP_RXCPL_STATUS 0x200C 19 #define RP_RXCPL_SOP BIT(0) 20 #define RP_RXCPL_EOP BIT(1) 21 #define RP_RXCPL_REG 0x2008 22 #define P2A_INT_STATUS 0x3060 23 #define P2A_INT_STS_ALL 0xf 24 #define P2A_INT_ENABLE 0x3070 25 #define RP_CAP_OFFSET 0x70 26 27 /* TLP configuration type 0 and 1 */ 28 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ 29 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ 30 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ 31 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ 32 #define TLP_PAYLOAD_SIZE 0x01 33 #define TLP_READ_TAG 0x1d 34 #define TLP_WRITE_TAG 0x10 35 #define RP_DEVFN 0 36 37 #define RP_CFG_ADDR(pcie, reg) \ 38 ((pcie->hip_base) + (reg) + (1 << 20)) 39 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) 40 41 #define TLP_CFGRD_DW0(pcie, bus) \ 42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \ 43 : TLP_FMTTYPE_CFGRD1) << 24) | \ 44 TLP_PAYLOAD_SIZE) 45 46 #define TLP_CFGWR_DW0(pcie, bus) \ 47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \ 48 : TLP_FMTTYPE_CFGWR1) << 24) | \ 49 TLP_PAYLOAD_SIZE) 50 51 #define TLP_CFG_DW1(pcie, tag, be) \ 52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be)) 53 #define TLP_CFG_DW2(bus, dev, fn, offset) \ 54 (((bus) << 24) | ((dev) << 19) | ((fn) << 16) | (offset)) 55 56 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) 57 #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) 58 #define TLP_HDR_SIZE 3 59 #define TLP_LOOP 500 60 #define DWORD_MASK 3 61 62 #define IS_ROOT_PORT(pcie, bdf) \ 63 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) 64 65 #define PCI_EXP_LNKSTA 18 /* Link Status */ 66 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 67 68 /** 69 * struct intel_fpga_pcie - Intel FPGA PCIe controller state 70 * @bus: Pointer to the PCI bus 71 * @cra_base: The base address of CRA register space 72 * @hip_base: The base address of Rootport configuration space 73 * @first_busno: This driver supports multiple PCIe controllers. 74 * first_busno stores the bus number of the PCIe root-port 75 * number which may vary depending on the PCIe setup. 76 */ 77 struct intel_fpga_pcie { 78 struct udevice *bus; 79 void __iomem *cra_base; 80 void __iomem *hip_base; 81 int first_busno; 82 }; 83 84 /** 85 * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the 86 * translation from PCI bus to native BUS. Entire DDR region is mapped 87 * into PCIe space using these registers, so it can be reached by DMA from 88 * EP devices. 89 * The BAR0 of bridge should be hidden during enumeration to avoid the 90 * sizing and resource allocation by PCIe core. 91 */ 92 static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie, 93 pci_dev_t bdf, int offset) 94 { 95 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 && 96 PCI_FUNC(bdf) == 0 && offset == PCI_BASE_ADDRESS_0) 97 return true; 98 99 return false; 100 } 101 102 static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value, 103 const u32 reg) 104 { 105 writel(value, pcie->cra_base + reg); 106 } 107 108 static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg) 109 { 110 return readl(pcie->cra_base + reg); 111 } 112 113 static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie) 114 { 115 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) 116 & PCI_EXP_LNKSTA_DLLLA); 117 } 118 119 static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie, 120 pci_dev_t bdf) 121 { 122 /* If there is no link, then there is no device */ 123 if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie)) 124 return false; 125 126 /* access only one slot on each root port */ 127 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0) 128 return false; 129 130 if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0) 131 return false; 132 133 return true; 134 } 135 136 static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl) 137 { 138 cra_writel(pcie, reg0, RP_TX_REG0); 139 cra_writel(pcie, ctrl, RP_TX_CNTRL); 140 } 141 142 static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value) 143 { 144 int i; 145 u32 ctrl; 146 u32 comp_status; 147 u32 dw[4]; 148 u32 count = 0; 149 150 for (i = 0; i < TLP_LOOP; i++) { 151 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); 152 if (!(ctrl & RP_RXCPL_SOP)) 153 continue; 154 155 /* read first DW */ 156 dw[count++] = cra_readl(pcie, RP_RXCPL_REG); 157 158 /* Poll for EOP */ 159 for (i = 0; i < TLP_LOOP; i++) { 160 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); 161 dw[count++] = cra_readl(pcie, RP_RXCPL_REG); 162 if (ctrl & RP_RXCPL_EOP) { 163 comp_status = TLP_COMP_STATUS(dw[1]); 164 if (comp_status) 165 return -EFAULT; 166 167 if (value && 168 TLP_BYTE_COUNT(dw[1]) == sizeof(u32) && 169 count >= 3) 170 *value = dw[3]; 171 172 return 0; 173 } 174 } 175 176 udelay(5); 177 } 178 179 dev_err(pcie->dev, "read TLP packet timed out\n"); 180 return -ENODEV; 181 } 182 183 static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers, 184 u32 data) 185 { 186 tlp_write_tx(pcie, headers[0], RP_TX_SOP); 187 188 tlp_write_tx(pcie, headers[1], 0); 189 190 tlp_write_tx(pcie, headers[2], 0); 191 192 tlp_write_tx(pcie, data, RP_TX_EOP); 193 } 194 195 static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf, 196 int offset, u8 byte_en, u32 *value) 197 { 198 u32 headers[TLP_HDR_SIZE]; 199 u8 busno = PCI_BUS(bdf); 200 201 headers[0] = TLP_CFGRD_DW0(pcie, busno); 202 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en); 203 headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); 204 205 tlp_write_packet(pcie, headers, 0); 206 207 return tlp_read_packet(pcie, value); 208 } 209 210 static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf, 211 int offset, u8 byte_en, u32 value) 212 { 213 u32 headers[TLP_HDR_SIZE]; 214 u8 busno = PCI_BUS(bdf); 215 216 headers[0] = TLP_CFGWR_DW0(pcie, busno); 217 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en); 218 headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); 219 220 tlp_write_packet(pcie, headers, value); 221 222 return tlp_read_packet(pcie, NULL); 223 } 224 225 int intel_fpga_rp_conf_addr(struct udevice *bus, pci_dev_t bdf, 226 uint offset, void **paddress) 227 { 228 struct intel_fpga_pcie *pcie = dev_get_priv(bus); 229 230 *paddress = RP_CFG_ADDR(pcie, offset); 231 232 return 0; 233 } 234 235 static int intel_fpga_pcie_rp_rd_conf(struct udevice *bus, pci_dev_t bdf, 236 uint offset, ulong *valuep, 237 enum pci_size_t size) 238 { 239 return pci_generic_mmap_read_config(bus, intel_fpga_rp_conf_addr, 240 bdf, offset, valuep, size); 241 } 242 243 static int intel_fpga_pcie_rp_wr_conf(struct udevice *bus, pci_dev_t bdf, 244 uint offset, ulong value, 245 enum pci_size_t size) 246 { 247 int ret; 248 struct intel_fpga_pcie *pcie = dev_get_priv(bus); 249 250 ret = pci_generic_mmap_write_config(bus, intel_fpga_rp_conf_addr, 251 bdf, offset, value, size); 252 if (!ret) { 253 /* Monitor changes to PCI_PRIMARY_BUS register on root port 254 * and update local copy of root bus number accordingly. 255 */ 256 if (offset == PCI_PRIMARY_BUS) 257 pcie->first_busno = (u8)(value); 258 } 259 260 return ret; 261 } 262 263 static u8 pcie_get_byte_en(uint offset, enum pci_size_t size) 264 { 265 switch (size) { 266 case PCI_SIZE_8: 267 return 1 << (offset & 3); 268 case PCI_SIZE_16: 269 return 3 << (offset & 3); 270 default: 271 return 0xf; 272 } 273 } 274 275 static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie, 276 pci_dev_t bdf, uint offset, 277 ulong *valuep, enum pci_size_t size) 278 { 279 int ret; 280 u32 data; 281 u8 byte_en; 282 283 /* Uses memory mapped method to read rootport config registers */ 284 if (IS_ROOT_PORT(pcie, bdf)) 285 return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf, 286 offset, valuep, size); 287 288 byte_en = pcie_get_byte_en(offset, size); 289 ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK, 290 byte_en, &data); 291 if (ret) 292 return ret; 293 294 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n", 295 offset, size, data); 296 *valuep = pci_conv_32_to_size(data, offset, size); 297 298 return 0; 299 } 300 301 static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie, 302 pci_dev_t bdf, uint offset, 303 ulong value, enum pci_size_t size) 304 { 305 u32 data; 306 u8 byte_en; 307 308 dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n", 309 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 310 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", 311 offset, size, value); 312 313 /* Uses memory mapped method to read rootport config registers */ 314 if (IS_ROOT_PORT(pcie, bdf)) 315 return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset, 316 value, size); 317 318 byte_en = pcie_get_byte_en(offset, size); 319 data = pci_conv_size_to_32(0, value, offset, size); 320 321 return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK, 322 byte_en, data); 323 } 324 325 static int pcie_intel_fpga_read_config(struct udevice *bus, pci_dev_t bdf, 326 uint offset, ulong *valuep, 327 enum pci_size_t size) 328 { 329 struct intel_fpga_pcie *pcie = dev_get_priv(bus); 330 331 dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n", 332 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 333 334 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) { 335 *valuep = (u32)pci_get_ff(size); 336 return 0; 337 } 338 339 if (!intel_fpga_pcie_addr_valid(pcie, bdf)) { 340 *valuep = (u32)pci_get_ff(size); 341 return 0; 342 } 343 344 return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size); 345 } 346 347 static int pcie_intel_fpga_write_config(struct udevice *bus, pci_dev_t bdf, 348 uint offset, ulong value, 349 enum pci_size_t size) 350 { 351 struct intel_fpga_pcie *pcie = dev_get_priv(bus); 352 353 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) 354 return 0; 355 356 if (!intel_fpga_pcie_addr_valid(pcie, bdf)) 357 return 0; 358 359 return _pcie_intel_fpga_write_config(pcie, bdf, offset, value, 360 size); 361 } 362 363 static int pcie_intel_fpga_probe(struct udevice *dev) 364 { 365 struct intel_fpga_pcie *pcie = dev_get_priv(dev); 366 367 pcie->bus = pci_get_controller(dev); 368 pcie->first_busno = dev->seq; 369 370 /* clear all interrupts */ 371 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); 372 /* disable all interrupts */ 373 cra_writel(pcie, 0, P2A_INT_ENABLE); 374 375 return 0; 376 } 377 378 static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev) 379 { 380 struct intel_fpga_pcie *pcie = dev_get_priv(dev); 381 struct fdt_resource reg_res; 382 int node = dev_of_offset(dev); 383 int ret; 384 385 DECLARE_GLOBAL_DATA_PTR; 386 387 ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", 388 "Cra", ®_res); 389 if (ret) { 390 dev_err(dev, "resource \"Cra\" not found\n"); 391 return ret; 392 } 393 394 pcie->cra_base = map_physmem(reg_res.start, 395 fdt_resource_size(®_res), 396 MAP_NOCACHE); 397 398 ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names", 399 "Hip", ®_res); 400 if (ret) { 401 dev_err(dev, "resource \"Hip\" not found\n"); 402 return ret; 403 } 404 405 pcie->hip_base = map_physmem(reg_res.start, 406 fdt_resource_size(®_res), 407 MAP_NOCACHE); 408 409 return 0; 410 } 411 412 static const struct dm_pci_ops pcie_intel_fpga_ops = { 413 .read_config = pcie_intel_fpga_read_config, 414 .write_config = pcie_intel_fpga_write_config, 415 }; 416 417 static const struct udevice_id pcie_intel_fpga_ids[] = { 418 { .compatible = "altr,pcie-root-port-2.0" }, 419 {}, 420 }; 421 422 U_BOOT_DRIVER(pcie_intel_fpga) = { 423 .name = "pcie_intel_fpga", 424 .id = UCLASS_PCI, 425 .of_match = pcie_intel_fpga_ids, 426 .ops = &pcie_intel_fpga_ops, 427 .ofdata_to_platdata = pcie_intel_fpga_ofdata_to_platdata, 428 .probe = pcie_intel_fpga_probe, 429 .priv_auto_alloc_size = sizeof(struct intel_fpga_pcie), 430 }; 431
