1 #ifndef A5XX_XML 2 #define A5XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-12-19 18:19:46) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2018-01-03 15:58:51) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-12-19 18:19:46) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 146261 bytes, from 2018-01-03 15:58:51) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27) 20 21 Copyright (C) 2013-2018 by the following authors: 22 - Rob Clark <robdclark (at) gmail.com> (robclark) 23 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum a5xx_color_fmt { 48 RB5_A8_UNORM = 2, 49 RB5_R8_UNORM = 3, 50 RB5_R8_SNORM = 4, 51 RB5_R8_UINT = 5, 52 RB5_R8_SINT = 6, 53 RB5_R4G4B4A4_UNORM = 8, 54 RB5_R5G5B5A1_UNORM = 10, 55 RB5_R5G6B5_UNORM = 14, 56 RB5_R8G8_UNORM = 15, 57 RB5_R8G8_SNORM = 16, 58 RB5_R8G8_UINT = 17, 59 RB5_R8G8_SINT = 18, 60 RB5_R16_UNORM = 21, 61 RB5_R16_SNORM = 22, 62 RB5_R16_FLOAT = 23, 63 RB5_R16_UINT = 24, 64 RB5_R16_SINT = 25, 65 RB5_R8G8B8A8_UNORM = 48, 66 RB5_R8G8B8_UNORM = 49, 67 RB5_R8G8B8A8_SNORM = 50, 68 RB5_R8G8B8A8_UINT = 51, 69 RB5_R8G8B8A8_SINT = 52, 70 RB5_R10G10B10A2_UNORM = 55, 71 RB5_R10G10B10A2_UINT = 58, 72 RB5_R11G11B10_FLOAT = 66, 73 RB5_R16G16_UNORM = 67, 74 RB5_R16G16_SNORM = 68, 75 RB5_R16G16_FLOAT = 69, 76 RB5_R16G16_UINT = 70, 77 RB5_R16G16_SINT = 71, 78 RB5_R32_FLOAT = 74, 79 RB5_R32_UINT = 75, 80 RB5_R32_SINT = 76, 81 RB5_R16G16B16A16_UNORM = 96, 82 RB5_R16G16B16A16_SNORM = 97, 83 RB5_R16G16B16A16_FLOAT = 98, 84 RB5_R16G16B16A16_UINT = 99, 85 RB5_R16G16B16A16_SINT = 100, 86 RB5_R32G32_FLOAT = 103, 87 RB5_R32G32_UINT = 104, 88 RB5_R32G32_SINT = 105, 89 RB5_R32G32B32A32_FLOAT = 130, 90 RB5_R32G32B32A32_UINT = 131, 91 RB5_R32G32B32A32_SINT = 132, 92 }; 93 94 enum a5xx_tile_mode { 95 TILE5_LINEAR = 0, 96 TILE5_2 = 2, 97 TILE5_3 = 3, 98 }; 99 100 enum a5xx_vtx_fmt { 101 VFMT5_8_UNORM = 3, 102 VFMT5_8_SNORM = 4, 103 VFMT5_8_UINT = 5, 104 VFMT5_8_SINT = 6, 105 VFMT5_8_8_UNORM = 15, 106 VFMT5_8_8_SNORM = 16, 107 VFMT5_8_8_UINT = 17, 108 VFMT5_8_8_SINT = 18, 109 VFMT5_16_UNORM = 21, 110 VFMT5_16_SNORM = 22, 111 VFMT5_16_FLOAT = 23, 112 VFMT5_16_UINT = 24, 113 VFMT5_16_SINT = 25, 114 VFMT5_8_8_8_UNORM = 33, 115 VFMT5_8_8_8_SNORM = 34, 116 VFMT5_8_8_8_UINT = 35, 117 VFMT5_8_8_8_SINT = 36, 118 VFMT5_8_8_8_8_UNORM = 48, 119 VFMT5_8_8_8_8_SNORM = 50, 120 VFMT5_8_8_8_8_UINT = 51, 121 VFMT5_8_8_8_8_SINT = 52, 122 VFMT5_10_10_10_2_UNORM = 54, 123 VFMT5_10_10_10_2_SNORM = 57, 124 VFMT5_10_10_10_2_UINT = 58, 125 VFMT5_10_10_10_2_SINT = 59, 126 VFMT5_11_11_10_FLOAT = 66, 127 VFMT5_16_16_UNORM = 67, 128 VFMT5_16_16_SNORM = 68, 129 VFMT5_16_16_FLOAT = 69, 130 VFMT5_16_16_UINT = 70, 131 VFMT5_16_16_SINT = 71, 132 VFMT5_32_UNORM = 72, 133 VFMT5_32_SNORM = 73, 134 VFMT5_32_FLOAT = 74, 135 VFMT5_32_UINT = 75, 136 VFMT5_32_SINT = 76, 137 VFMT5_32_FIXED = 77, 138 VFMT5_16_16_16_UNORM = 88, 139 VFMT5_16_16_16_SNORM = 89, 140 VFMT5_16_16_16_FLOAT = 90, 141 VFMT5_16_16_16_UINT = 91, 142 VFMT5_16_16_16_SINT = 92, 143 VFMT5_16_16_16_16_UNORM = 96, 144 VFMT5_16_16_16_16_SNORM = 97, 145 VFMT5_16_16_16_16_FLOAT = 98, 146 VFMT5_16_16_16_16_UINT = 99, 147 VFMT5_16_16_16_16_SINT = 100, 148 VFMT5_32_32_UNORM = 101, 149 VFMT5_32_32_SNORM = 102, 150 VFMT5_32_32_FLOAT = 103, 151 VFMT5_32_32_UINT = 104, 152 VFMT5_32_32_SINT = 105, 153 VFMT5_32_32_FIXED = 106, 154 VFMT5_32_32_32_UNORM = 112, 155 VFMT5_32_32_32_SNORM = 113, 156 VFMT5_32_32_32_UINT = 114, 157 VFMT5_32_32_32_SINT = 115, 158 VFMT5_32_32_32_FLOAT = 116, 159 VFMT5_32_32_32_FIXED = 117, 160 VFMT5_32_32_32_32_UNORM = 128, 161 VFMT5_32_32_32_32_SNORM = 129, 162 VFMT5_32_32_32_32_FLOAT = 130, 163 VFMT5_32_32_32_32_UINT = 131, 164 VFMT5_32_32_32_32_SINT = 132, 165 VFMT5_32_32_32_32_FIXED = 133, 166 }; 167 168 enum a5xx_tex_fmt { 169 TFMT5_A8_UNORM = 2, 170 TFMT5_8_UNORM = 3, 171 TFMT5_8_SNORM = 4, 172 TFMT5_8_UINT = 5, 173 TFMT5_8_SINT = 6, 174 TFMT5_4_4_4_4_UNORM = 8, 175 TFMT5_5_5_5_1_UNORM = 10, 176 TFMT5_5_6_5_UNORM = 14, 177 TFMT5_8_8_UNORM = 15, 178 TFMT5_8_8_SNORM = 16, 179 TFMT5_8_8_UINT = 17, 180 TFMT5_8_8_SINT = 18, 181 TFMT5_L8_A8_UNORM = 19, 182 TFMT5_16_UNORM = 21, 183 TFMT5_16_SNORM = 22, 184 TFMT5_16_FLOAT = 23, 185 TFMT5_16_UINT = 24, 186 TFMT5_16_SINT = 25, 187 TFMT5_8_8_8_8_UNORM = 48, 188 TFMT5_8_8_8_UNORM = 49, 189 TFMT5_8_8_8_8_SNORM = 50, 190 TFMT5_8_8_8_8_UINT = 51, 191 TFMT5_8_8_8_8_SINT = 52, 192 TFMT5_9_9_9_E5_FLOAT = 53, 193 TFMT5_10_10_10_2_UNORM = 54, 194 TFMT5_10_10_10_2_UINT = 58, 195 TFMT5_11_11_10_FLOAT = 66, 196 TFMT5_16_16_UNORM = 67, 197 TFMT5_16_16_SNORM = 68, 198 TFMT5_16_16_FLOAT = 69, 199 TFMT5_16_16_UINT = 70, 200 TFMT5_16_16_SINT = 71, 201 TFMT5_32_FLOAT = 74, 202 TFMT5_32_UINT = 75, 203 TFMT5_32_SINT = 76, 204 TFMT5_16_16_16_16_UNORM = 96, 205 TFMT5_16_16_16_16_SNORM = 97, 206 TFMT5_16_16_16_16_FLOAT = 98, 207 TFMT5_16_16_16_16_UINT = 99, 208 TFMT5_16_16_16_16_SINT = 100, 209 TFMT5_32_32_FLOAT = 103, 210 TFMT5_32_32_UINT = 104, 211 TFMT5_32_32_SINT = 105, 212 TFMT5_32_32_32_UINT = 114, 213 TFMT5_32_32_32_SINT = 115, 214 TFMT5_32_32_32_FLOAT = 116, 215 TFMT5_32_32_32_32_FLOAT = 130, 216 TFMT5_32_32_32_32_UINT = 131, 217 TFMT5_32_32_32_32_SINT = 132, 218 TFMT5_X8Z24_UNORM = 160, 219 TFMT5_ETC2_RG11_UNORM = 171, 220 TFMT5_ETC2_RG11_SNORM = 172, 221 TFMT5_ETC2_R11_UNORM = 173, 222 TFMT5_ETC2_R11_SNORM = 174, 223 TFMT5_ETC1 = 175, 224 TFMT5_ETC2_RGB8 = 176, 225 TFMT5_ETC2_RGBA8 = 177, 226 TFMT5_ETC2_RGB8A1 = 178, 227 TFMT5_DXT1 = 179, 228 TFMT5_DXT3 = 180, 229 TFMT5_DXT5 = 181, 230 TFMT5_RGTC1_UNORM = 183, 231 TFMT5_RGTC1_SNORM = 184, 232 TFMT5_RGTC2_UNORM = 187, 233 TFMT5_RGTC2_SNORM = 188, 234 TFMT5_BPTC_UFLOAT = 190, 235 TFMT5_BPTC_FLOAT = 191, 236 TFMT5_BPTC = 192, 237 TFMT5_ASTC_4x4 = 193, 238 TFMT5_ASTC_5x4 = 194, 239 TFMT5_ASTC_5x5 = 195, 240 TFMT5_ASTC_6x5 = 196, 241 TFMT5_ASTC_6x6 = 197, 242 TFMT5_ASTC_8x5 = 198, 243 TFMT5_ASTC_8x6 = 199, 244 TFMT5_ASTC_8x8 = 200, 245 TFMT5_ASTC_10x5 = 201, 246 TFMT5_ASTC_10x6 = 202, 247 TFMT5_ASTC_10x8 = 203, 248 TFMT5_ASTC_10x10 = 204, 249 TFMT5_ASTC_12x10 = 205, 250 TFMT5_ASTC_12x12 = 206, 251 }; 252 253 enum a5xx_tex_fetchsize { 254 TFETCH5_1_BYTE = 0, 255 TFETCH5_2_BYTE = 1, 256 TFETCH5_4_BYTE = 2, 257 TFETCH5_8_BYTE = 3, 258 TFETCH5_16_BYTE = 4, 259 }; 260 261 enum a5xx_depth_format { 262 DEPTH5_NONE = 0, 263 DEPTH5_16 = 1, 264 DEPTH5_24_8 = 2, 265 DEPTH5_32 = 4, 266 }; 267 268 enum a5xx_blit_buf { 269 BLIT_MRT0 = 0, 270 BLIT_MRT1 = 1, 271 BLIT_MRT2 = 2, 272 BLIT_MRT3 = 3, 273 BLIT_MRT4 = 4, 274 BLIT_MRT5 = 5, 275 BLIT_MRT6 = 6, 276 BLIT_MRT7 = 7, 277 BLIT_ZS = 8, 278 BLIT_S = 9, 279 }; 280 281 enum a5xx_cp_perfcounter_select { 282 PERF_CP_ALWAYS_COUNT = 0, 283 PERF_CP_BUSY_GFX_CORE_IDLE = 1, 284 PERF_CP_BUSY_CYCLES = 2, 285 PERF_CP_PFP_IDLE = 3, 286 PERF_CP_PFP_BUSY_WORKING = 4, 287 PERF_CP_PFP_STALL_CYCLES_ANY = 5, 288 PERF_CP_PFP_STARVE_CYCLES_ANY = 6, 289 PERF_CP_PFP_ICACHE_MISS = 7, 290 PERF_CP_PFP_ICACHE_HIT = 8, 291 PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 292 PERF_CP_ME_BUSY_WORKING = 10, 293 PERF_CP_ME_IDLE = 11, 294 PERF_CP_ME_STARVE_CYCLES_ANY = 12, 295 PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13, 296 PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14, 297 PERF_CP_ME_FIFO_FULL_ME_BUSY = 15, 298 PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16, 299 PERF_CP_ME_STALL_CYCLES_ANY = 17, 300 PERF_CP_ME_ICACHE_MISS = 18, 301 PERF_CP_ME_ICACHE_HIT = 19, 302 PERF_CP_NUM_PREEMPTIONS = 20, 303 PERF_CP_PREEMPTION_REACTION_DELAY = 21, 304 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22, 305 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23, 306 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24, 307 PERF_CP_PREDICATED_DRAWS_KILLED = 25, 308 PERF_CP_MODE_SWITCH = 26, 309 PERF_CP_ZPASS_DONE = 27, 310 PERF_CP_CONTEXT_DONE = 28, 311 PERF_CP_CACHE_FLUSH = 29, 312 PERF_CP_LONG_PREEMPTIONS = 30, 313 }; 314 315 enum a5xx_rbbm_perfcounter_select { 316 PERF_RBBM_ALWAYS_COUNT = 0, 317 PERF_RBBM_ALWAYS_ON = 1, 318 PERF_RBBM_TSE_BUSY = 2, 319 PERF_RBBM_RAS_BUSY = 3, 320 PERF_RBBM_PC_DCALL_BUSY = 4, 321 PERF_RBBM_PC_VSD_BUSY = 5, 322 PERF_RBBM_STATUS_MASKED = 6, 323 PERF_RBBM_COM_BUSY = 7, 324 PERF_RBBM_DCOM_BUSY = 8, 325 PERF_RBBM_VBIF_BUSY = 9, 326 PERF_RBBM_VSC_BUSY = 10, 327 PERF_RBBM_TESS_BUSY = 11, 328 PERF_RBBM_UCHE_BUSY = 12, 329 PERF_RBBM_HLSQ_BUSY = 13, 330 }; 331 332 enum a5xx_pc_perfcounter_select { 333 PERF_PC_BUSY_CYCLES = 0, 334 PERF_PC_WORKING_CYCLES = 1, 335 PERF_PC_STALL_CYCLES_VFD = 2, 336 PERF_PC_STALL_CYCLES_TSE = 3, 337 PERF_PC_STALL_CYCLES_VPC = 4, 338 PERF_PC_STALL_CYCLES_UCHE = 5, 339 PERF_PC_STALL_CYCLES_TESS = 6, 340 PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 341 PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 342 PERF_PC_PASS1_TF_STALL_CYCLES = 9, 343 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 344 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 345 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 346 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 347 PERF_PC_STARVE_CYCLES_DI = 14, 348 PERF_PC_VIS_STREAMS_LOADED = 15, 349 PERF_PC_INSTANCES = 16, 350 PERF_PC_VPC_PRIMITIVES = 17, 351 PERF_PC_DEAD_PRIM = 18, 352 PERF_PC_LIVE_PRIM = 19, 353 PERF_PC_VERTEX_HITS = 20, 354 PERF_PC_IA_VERTICES = 21, 355 PERF_PC_IA_PRIMITIVES = 22, 356 PERF_PC_GS_PRIMITIVES = 23, 357 PERF_PC_HS_INVOCATIONS = 24, 358 PERF_PC_DS_INVOCATIONS = 25, 359 PERF_PC_VS_INVOCATIONS = 26, 360 PERF_PC_GS_INVOCATIONS = 27, 361 PERF_PC_DS_PRIMITIVES = 28, 362 PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 363 PERF_PC_3D_DRAWCALLS = 30, 364 PERF_PC_2D_DRAWCALLS = 31, 365 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 366 PERF_TESS_BUSY_CYCLES = 33, 367 PERF_TESS_WORKING_CYCLES = 34, 368 PERF_TESS_STALL_CYCLES_PC = 35, 369 PERF_TESS_STARVE_CYCLES_PC = 36, 370 }; 371 372 enum a5xx_vfd_perfcounter_select { 373 PERF_VFD_BUSY_CYCLES = 0, 374 PERF_VFD_STALL_CYCLES_UCHE = 1, 375 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 376 PERF_VFD_STALL_CYCLES_MISS_VB = 3, 377 PERF_VFD_STALL_CYCLES_MISS_Q = 4, 378 PERF_VFD_STALL_CYCLES_SP_INFO = 5, 379 PERF_VFD_STALL_CYCLES_SP_ATTR = 6, 380 PERF_VFD_STALL_CYCLES_VFDP_VB = 7, 381 PERF_VFD_STALL_CYCLES_VFDP_Q = 8, 382 PERF_VFD_DECODER_PACKER_STALL = 9, 383 PERF_VFD_STARVE_CYCLES_UCHE = 10, 384 PERF_VFD_RBUFFER_FULL = 11, 385 PERF_VFD_ATTR_INFO_FIFO_FULL = 12, 386 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13, 387 PERF_VFD_NUM_ATTRIBUTES = 14, 388 PERF_VFD_INSTRUCTIONS = 15, 389 PERF_VFD_UPPER_SHADER_FIBERS = 16, 390 PERF_VFD_LOWER_SHADER_FIBERS = 17, 391 PERF_VFD_MODE_0_FIBERS = 18, 392 PERF_VFD_MODE_1_FIBERS = 19, 393 PERF_VFD_MODE_2_FIBERS = 20, 394 PERF_VFD_MODE_3_FIBERS = 21, 395 PERF_VFD_MODE_4_FIBERS = 22, 396 PERF_VFD_TOTAL_VERTICES = 23, 397 PERF_VFD_NUM_ATTR_MISS = 24, 398 PERF_VFD_1_BURST_REQ = 25, 399 PERF_VFDP_STALL_CYCLES_VFD = 26, 400 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27, 401 PERF_VFDP_STALL_CYCLES_VFD_PROG = 28, 402 PERF_VFDP_STARVE_CYCLES_PC = 29, 403 PERF_VFDP_VS_STAGE_32_WAVES = 30, 404 }; 405 406 enum a5xx_hlsq_perfcounter_select { 407 PERF_HLSQ_BUSY_CYCLES = 0, 408 PERF_HLSQ_STALL_CYCLES_UCHE = 1, 409 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 410 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 411 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 412 PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 413 PERF_HLSQ_FS_STAGE_32_WAVES = 6, 414 PERF_HLSQ_FS_STAGE_64_WAVES = 7, 415 PERF_HLSQ_QUADS = 8, 416 PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9, 417 PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10, 418 PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11, 419 PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12, 420 PERF_HLSQ_CS_INVOCATIONS = 13, 421 PERF_HLSQ_COMPUTE_DRAWCALLS = 14, 422 }; 423 424 enum a5xx_vpc_perfcounter_select { 425 PERF_VPC_BUSY_CYCLES = 0, 426 PERF_VPC_WORKING_CYCLES = 1, 427 PERF_VPC_STALL_CYCLES_UCHE = 2, 428 PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 429 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 430 PERF_VPC_STALL_CYCLES_PC = 5, 431 PERF_VPC_STALL_CYCLES_SP_LM = 6, 432 PERF_VPC_POS_EXPORT_STALL_CYCLES = 7, 433 PERF_VPC_STARVE_CYCLES_SP = 8, 434 PERF_VPC_STARVE_CYCLES_LRZ = 9, 435 PERF_VPC_PC_PRIMITIVES = 10, 436 PERF_VPC_SP_COMPONENTS = 11, 437 PERF_VPC_SP_LM_PRIMITIVES = 12, 438 PERF_VPC_SP_LM_COMPONENTS = 13, 439 PERF_VPC_SP_LM_DWORDS = 14, 440 PERF_VPC_STREAMOUT_COMPONENTS = 15, 441 PERF_VPC_GRANT_PHASES = 16, 442 }; 443 444 enum a5xx_tse_perfcounter_select { 445 PERF_TSE_BUSY_CYCLES = 0, 446 PERF_TSE_CLIPPING_CYCLES = 1, 447 PERF_TSE_STALL_CYCLES_RAS = 2, 448 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 449 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 450 PERF_TSE_STARVE_CYCLES_PC = 5, 451 PERF_TSE_INPUT_PRIM = 6, 452 PERF_TSE_INPUT_NULL_PRIM = 7, 453 PERF_TSE_TRIVAL_REJ_PRIM = 8, 454 PERF_TSE_CLIPPED_PRIM = 9, 455 PERF_TSE_ZERO_AREA_PRIM = 10, 456 PERF_TSE_FACENESS_CULLED_PRIM = 11, 457 PERF_TSE_ZERO_PIXEL_PRIM = 12, 458 PERF_TSE_OUTPUT_NULL_PRIM = 13, 459 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 460 PERF_TSE_CINVOCATION = 15, 461 PERF_TSE_CPRIMITIVES = 16, 462 PERF_TSE_2D_INPUT_PRIM = 17, 463 PERF_TSE_2D_ALIVE_CLCLES = 18, 464 }; 465 466 enum a5xx_ras_perfcounter_select { 467 PERF_RAS_BUSY_CYCLES = 0, 468 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 469 PERF_RAS_STALL_CYCLES_LRZ = 2, 470 PERF_RAS_STARVE_CYCLES_TSE = 3, 471 PERF_RAS_SUPER_TILES = 4, 472 PERF_RAS_8X4_TILES = 5, 473 PERF_RAS_MASKGEN_ACTIVE = 6, 474 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 475 PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 476 PERF_RAS_PRIM_KILLED_INVISILBE = 9, 477 }; 478 479 enum a5xx_lrz_perfcounter_select { 480 PERF_LRZ_BUSY_CYCLES = 0, 481 PERF_LRZ_STARVE_CYCLES_RAS = 1, 482 PERF_LRZ_STALL_CYCLES_RB = 2, 483 PERF_LRZ_STALL_CYCLES_VSC = 3, 484 PERF_LRZ_STALL_CYCLES_VPC = 4, 485 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 486 PERF_LRZ_STALL_CYCLES_UCHE = 6, 487 PERF_LRZ_LRZ_READ = 7, 488 PERF_LRZ_LRZ_WRITE = 8, 489 PERF_LRZ_READ_LATENCY = 9, 490 PERF_LRZ_MERGE_CACHE_UPDATING = 10, 491 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 492 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 493 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 494 PERF_LRZ_FULL_8X8_TILES = 14, 495 PERF_LRZ_PARTIAL_8X8_TILES = 15, 496 PERF_LRZ_TILE_KILLED = 16, 497 PERF_LRZ_TOTAL_PIXEL = 17, 498 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 499 }; 500 501 enum a5xx_uche_perfcounter_select { 502 PERF_UCHE_BUSY_CYCLES = 0, 503 PERF_UCHE_STALL_CYCLES_VBIF = 1, 504 PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 505 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 506 PERF_UCHE_VBIF_READ_BEATS_TP = 4, 507 PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 508 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 509 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 510 PERF_UCHE_VBIF_READ_BEATS_SP = 8, 511 PERF_UCHE_READ_REQUESTS_TP = 9, 512 PERF_UCHE_READ_REQUESTS_VFD = 10, 513 PERF_UCHE_READ_REQUESTS_HLSQ = 11, 514 PERF_UCHE_READ_REQUESTS_LRZ = 12, 515 PERF_UCHE_READ_REQUESTS_SP = 13, 516 PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 517 PERF_UCHE_WRITE_REQUESTS_SP = 15, 518 PERF_UCHE_WRITE_REQUESTS_VPC = 16, 519 PERF_UCHE_WRITE_REQUESTS_VSC = 17, 520 PERF_UCHE_EVICTS = 18, 521 PERF_UCHE_BANK_REQ0 = 19, 522 PERF_UCHE_BANK_REQ1 = 20, 523 PERF_UCHE_BANK_REQ2 = 21, 524 PERF_UCHE_BANK_REQ3 = 22, 525 PERF_UCHE_BANK_REQ4 = 23, 526 PERF_UCHE_BANK_REQ5 = 24, 527 PERF_UCHE_BANK_REQ6 = 25, 528 PERF_UCHE_BANK_REQ7 = 26, 529 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 530 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 531 PERF_UCHE_GMEM_READ_BEATS = 29, 532 PERF_UCHE_FLAG_COUNT = 30, 533 }; 534 535 enum a5xx_tp_perfcounter_select { 536 PERF_TP_BUSY_CYCLES = 0, 537 PERF_TP_STALL_CYCLES_UCHE = 1, 538 PERF_TP_LATENCY_CYCLES = 2, 539 PERF_TP_LATENCY_TRANS = 3, 540 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 541 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 542 PERF_TP_L1_CACHELINE_REQUESTS = 6, 543 PERF_TP_L1_CACHELINE_MISSES = 7, 544 PERF_TP_SP_TP_TRANS = 8, 545 PERF_TP_TP_SP_TRANS = 9, 546 PERF_TP_OUTPUT_PIXELS = 10, 547 PERF_TP_FILTER_WORKLOAD_16BIT = 11, 548 PERF_TP_FILTER_WORKLOAD_32BIT = 12, 549 PERF_TP_QUADS_RECEIVED = 13, 550 PERF_TP_QUADS_OFFSET = 14, 551 PERF_TP_QUADS_SHADOW = 15, 552 PERF_TP_QUADS_ARRAY = 16, 553 PERF_TP_QUADS_GRADIENT = 17, 554 PERF_TP_QUADS_1D = 18, 555 PERF_TP_QUADS_2D = 19, 556 PERF_TP_QUADS_BUFFER = 20, 557 PERF_TP_QUADS_3D = 21, 558 PERF_TP_QUADS_CUBE = 22, 559 PERF_TP_STATE_CACHE_REQUESTS = 23, 560 PERF_TP_STATE_CACHE_MISSES = 24, 561 PERF_TP_DIVERGENT_QUADS_RECEIVED = 25, 562 PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26, 563 PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27, 564 PERF_TP_PRT_NON_RESIDENT_EVENTS = 28, 565 PERF_TP_OUTPUT_PIXELS_POINT = 29, 566 PERF_TP_OUTPUT_PIXELS_BILINEAR = 30, 567 PERF_TP_OUTPUT_PIXELS_MIP = 31, 568 PERF_TP_OUTPUT_PIXELS_ANISO = 32, 569 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33, 570 PERF_TP_FLAG_CACHE_REQUESTS = 34, 571 PERF_TP_FLAG_CACHE_MISSES = 35, 572 PERF_TP_L1_5_L2_REQUESTS = 36, 573 PERF_TP_2D_OUTPUT_PIXELS = 37, 574 PERF_TP_2D_OUTPUT_PIXELS_POINT = 38, 575 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39, 576 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40, 577 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41, 578 }; 579 580 enum a5xx_sp_perfcounter_select { 581 PERF_SP_BUSY_CYCLES = 0, 582 PERF_SP_ALU_WORKING_CYCLES = 1, 583 PERF_SP_EFU_WORKING_CYCLES = 2, 584 PERF_SP_STALL_CYCLES_VPC = 3, 585 PERF_SP_STALL_CYCLES_TP = 4, 586 PERF_SP_STALL_CYCLES_UCHE = 5, 587 PERF_SP_STALL_CYCLES_RB = 6, 588 PERF_SP_SCHEDULER_NON_WORKING = 7, 589 PERF_SP_WAVE_CONTEXTS = 8, 590 PERF_SP_WAVE_CONTEXT_CYCLES = 9, 591 PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 592 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 593 PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 594 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 595 PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 596 PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 597 PERF_SP_WAVE_CTRL_CYCLES = 16, 598 PERF_SP_WAVE_LOAD_CYCLES = 17, 599 PERF_SP_WAVE_EMIT_CYCLES = 18, 600 PERF_SP_WAVE_NOP_CYCLES = 19, 601 PERF_SP_WAVE_WAIT_CYCLES = 20, 602 PERF_SP_WAVE_FETCH_CYCLES = 21, 603 PERF_SP_WAVE_IDLE_CYCLES = 22, 604 PERF_SP_WAVE_END_CYCLES = 23, 605 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 606 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 607 PERF_SP_WAVE_JOIN_CYCLES = 26, 608 PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 609 PERF_SP_LM_STORE_INSTRUCTIONS = 28, 610 PERF_SP_LM_ATOMICS = 29, 611 PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 612 PERF_SP_GM_STORE_INSTRUCTIONS = 31, 613 PERF_SP_GM_ATOMICS = 32, 614 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 615 PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34, 616 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35, 617 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36, 618 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37, 619 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38, 620 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39, 621 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40, 622 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41, 623 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42, 624 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43, 625 PERF_SP_VS_INSTRUCTIONS = 44, 626 PERF_SP_FS_INSTRUCTIONS = 45, 627 PERF_SP_ADDR_LOCK_COUNT = 46, 628 PERF_SP_UCHE_READ_TRANS = 47, 629 PERF_SP_UCHE_WRITE_TRANS = 48, 630 PERF_SP_EXPORT_VPC_TRANS = 49, 631 PERF_SP_EXPORT_RB_TRANS = 50, 632 PERF_SP_PIXELS_KILLED = 51, 633 PERF_SP_ICL1_REQUESTS = 52, 634 PERF_SP_ICL1_MISSES = 53, 635 PERF_SP_ICL0_REQUESTS = 54, 636 PERF_SP_ICL0_MISSES = 55, 637 PERF_SP_HS_INSTRUCTIONS = 56, 638 PERF_SP_DS_INSTRUCTIONS = 57, 639 PERF_SP_GS_INSTRUCTIONS = 58, 640 PERF_SP_CS_INSTRUCTIONS = 59, 641 PERF_SP_GPR_READ = 60, 642 PERF_SP_GPR_WRITE = 61, 643 PERF_SP_LM_CH0_REQUESTS = 62, 644 PERF_SP_LM_CH1_REQUESTS = 63, 645 PERF_SP_LM_BANK_CONFLICTS = 64, 646 }; 647 648 enum a5xx_rb_perfcounter_select { 649 PERF_RB_BUSY_CYCLES = 0, 650 PERF_RB_STALL_CYCLES_CCU = 1, 651 PERF_RB_STALL_CYCLES_HLSQ = 2, 652 PERF_RB_STALL_CYCLES_FIFO0_FULL = 3, 653 PERF_RB_STALL_CYCLES_FIFO1_FULL = 4, 654 PERF_RB_STALL_CYCLES_FIFO2_FULL = 5, 655 PERF_RB_STARVE_CYCLES_SP = 6, 656 PERF_RB_STARVE_CYCLES_LRZ_TILE = 7, 657 PERF_RB_STARVE_CYCLES_CCU = 8, 658 PERF_RB_STARVE_CYCLES_Z_PLANE = 9, 659 PERF_RB_STARVE_CYCLES_BARY_PLANE = 10, 660 PERF_RB_Z_WORKLOAD = 11, 661 PERF_RB_HLSQ_ACTIVE = 12, 662 PERF_RB_Z_READ = 13, 663 PERF_RB_Z_WRITE = 14, 664 PERF_RB_C_READ = 15, 665 PERF_RB_C_WRITE = 16, 666 PERF_RB_TOTAL_PASS = 17, 667 PERF_RB_Z_PASS = 18, 668 PERF_RB_Z_FAIL = 19, 669 PERF_RB_S_FAIL = 20, 670 PERF_RB_BLENDED_FXP_COMPONENTS = 21, 671 PERF_RB_BLENDED_FP16_COMPONENTS = 22, 672 RB_RESERVED = 23, 673 PERF_RB_2D_ALIVE_CYCLES = 24, 674 PERF_RB_2D_STALL_CYCLES_A2D = 25, 675 PERF_RB_2D_STARVE_CYCLES_SRC = 26, 676 PERF_RB_2D_STARVE_CYCLES_SP = 27, 677 PERF_RB_2D_STARVE_CYCLES_DST = 28, 678 PERF_RB_2D_VALID_PIXELS = 29, 679 }; 680 681 enum a5xx_rb_samples_perfcounter_select { 682 TOTAL_SAMPLES = 0, 683 ZPASS_SAMPLES = 1, 684 ZFAIL_SAMPLES = 2, 685 SFAIL_SAMPLES = 3, 686 }; 687 688 enum a5xx_vsc_perfcounter_select { 689 PERF_VSC_BUSY_CYCLES = 0, 690 PERF_VSC_WORKING_CYCLES = 1, 691 PERF_VSC_STALL_CYCLES_UCHE = 2, 692 PERF_VSC_EOT_NUM = 3, 693 }; 694 695 enum a5xx_ccu_perfcounter_select { 696 PERF_CCU_BUSY_CYCLES = 0, 697 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 698 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 699 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 700 PERF_CCU_DEPTH_BLOCKS = 4, 701 PERF_CCU_COLOR_BLOCKS = 5, 702 PERF_CCU_DEPTH_BLOCK_HIT = 6, 703 PERF_CCU_COLOR_BLOCK_HIT = 7, 704 PERF_CCU_PARTIAL_BLOCK_READ = 8, 705 PERF_CCU_GMEM_READ = 9, 706 PERF_CCU_GMEM_WRITE = 10, 707 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 708 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 709 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 710 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 711 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 712 PERF_CCU_COLOR_READ_FLAG0_COUNT = 16, 713 PERF_CCU_COLOR_READ_FLAG1_COUNT = 17, 714 PERF_CCU_COLOR_READ_FLAG2_COUNT = 18, 715 PERF_CCU_COLOR_READ_FLAG3_COUNT = 19, 716 PERF_CCU_COLOR_READ_FLAG4_COUNT = 20, 717 PERF_CCU_2D_BUSY_CYCLES = 21, 718 PERF_CCU_2D_RD_REQ = 22, 719 PERF_CCU_2D_WR_REQ = 23, 720 PERF_CCU_2D_REORDER_STARVE_CYCLES = 24, 721 PERF_CCU_2D_PIXELS = 25, 722 }; 723 724 enum a5xx_cmp_perfcounter_select { 725 PERF_CMPDECMP_STALL_CYCLES_VBIF = 0, 726 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 727 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 728 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 729 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 730 PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 731 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 732 PERF_CMPDECMP_VBIF_READ_DATA = 7, 733 PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 734 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 735 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 736 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 737 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 738 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 739 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 740 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15, 741 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16, 742 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17, 743 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18, 744 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19, 745 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20, 746 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21, 747 PERF_CMPDECMP_2D_RD_DATA = 22, 748 PERF_CMPDECMP_2D_WR_DATA = 23, 749 }; 750 751 enum a5xx_vbif_perfcounter_select { 752 AXI_READ_REQUESTS_ID_0 = 0, 753 AXI_READ_REQUESTS_ID_1 = 1, 754 AXI_READ_REQUESTS_ID_2 = 2, 755 AXI_READ_REQUESTS_ID_3 = 3, 756 AXI_READ_REQUESTS_ID_4 = 4, 757 AXI_READ_REQUESTS_ID_5 = 5, 758 AXI_READ_REQUESTS_ID_6 = 6, 759 AXI_READ_REQUESTS_ID_7 = 7, 760 AXI_READ_REQUESTS_ID_8 = 8, 761 AXI_READ_REQUESTS_ID_9 = 9, 762 AXI_READ_REQUESTS_ID_10 = 10, 763 AXI_READ_REQUESTS_ID_11 = 11, 764 AXI_READ_REQUESTS_ID_12 = 12, 765 AXI_READ_REQUESTS_ID_13 = 13, 766 AXI_READ_REQUESTS_ID_14 = 14, 767 AXI_READ_REQUESTS_ID_15 = 15, 768 AXI0_READ_REQUESTS_TOTAL = 16, 769 AXI1_READ_REQUESTS_TOTAL = 17, 770 AXI2_READ_REQUESTS_TOTAL = 18, 771 AXI3_READ_REQUESTS_TOTAL = 19, 772 AXI_READ_REQUESTS_TOTAL = 20, 773 AXI_WRITE_REQUESTS_ID_0 = 21, 774 AXI_WRITE_REQUESTS_ID_1 = 22, 775 AXI_WRITE_REQUESTS_ID_2 = 23, 776 AXI_WRITE_REQUESTS_ID_3 = 24, 777 AXI_WRITE_REQUESTS_ID_4 = 25, 778 AXI_WRITE_REQUESTS_ID_5 = 26, 779 AXI_WRITE_REQUESTS_ID_6 = 27, 780 AXI_WRITE_REQUESTS_ID_7 = 28, 781 AXI_WRITE_REQUESTS_ID_8 = 29, 782 AXI_WRITE_REQUESTS_ID_9 = 30, 783 AXI_WRITE_REQUESTS_ID_10 = 31, 784 AXI_WRITE_REQUESTS_ID_11 = 32, 785 AXI_WRITE_REQUESTS_ID_12 = 33, 786 AXI_WRITE_REQUESTS_ID_13 = 34, 787 AXI_WRITE_REQUESTS_ID_14 = 35, 788 AXI_WRITE_REQUESTS_ID_15 = 36, 789 AXI0_WRITE_REQUESTS_TOTAL = 37, 790 AXI1_WRITE_REQUESTS_TOTAL = 38, 791 AXI2_WRITE_REQUESTS_TOTAL = 39, 792 AXI3_WRITE_REQUESTS_TOTAL = 40, 793 AXI_WRITE_REQUESTS_TOTAL = 41, 794 AXI_TOTAL_REQUESTS = 42, 795 AXI_READ_DATA_BEATS_ID_0 = 43, 796 AXI_READ_DATA_BEATS_ID_1 = 44, 797 AXI_READ_DATA_BEATS_ID_2 = 45, 798 AXI_READ_DATA_BEATS_ID_3 = 46, 799 AXI_READ_DATA_BEATS_ID_4 = 47, 800 AXI_READ_DATA_BEATS_ID_5 = 48, 801 AXI_READ_DATA_BEATS_ID_6 = 49, 802 AXI_READ_DATA_BEATS_ID_7 = 50, 803 AXI_READ_DATA_BEATS_ID_8 = 51, 804 AXI_READ_DATA_BEATS_ID_9 = 52, 805 AXI_READ_DATA_BEATS_ID_10 = 53, 806 AXI_READ_DATA_BEATS_ID_11 = 54, 807 AXI_READ_DATA_BEATS_ID_12 = 55, 808 AXI_READ_DATA_BEATS_ID_13 = 56, 809 AXI_READ_DATA_BEATS_ID_14 = 57, 810 AXI_READ_DATA_BEATS_ID_15 = 58, 811 AXI0_READ_DATA_BEATS_TOTAL = 59, 812 AXI1_READ_DATA_BEATS_TOTAL = 60, 813 AXI2_READ_DATA_BEATS_TOTAL = 61, 814 AXI3_READ_DATA_BEATS_TOTAL = 62, 815 AXI_READ_DATA_BEATS_TOTAL = 63, 816 AXI_WRITE_DATA_BEATS_ID_0 = 64, 817 AXI_WRITE_DATA_BEATS_ID_1 = 65, 818 AXI_WRITE_DATA_BEATS_ID_2 = 66, 819 AXI_WRITE_DATA_BEATS_ID_3 = 67, 820 AXI_WRITE_DATA_BEATS_ID_4 = 68, 821 AXI_WRITE_DATA_BEATS_ID_5 = 69, 822 AXI_WRITE_DATA_BEATS_ID_6 = 70, 823 AXI_WRITE_DATA_BEATS_ID_7 = 71, 824 AXI_WRITE_DATA_BEATS_ID_8 = 72, 825 AXI_WRITE_DATA_BEATS_ID_9 = 73, 826 AXI_WRITE_DATA_BEATS_ID_10 = 74, 827 AXI_WRITE_DATA_BEATS_ID_11 = 75, 828 AXI_WRITE_DATA_BEATS_ID_12 = 76, 829 AXI_WRITE_DATA_BEATS_ID_13 = 77, 830 AXI_WRITE_DATA_BEATS_ID_14 = 78, 831 AXI_WRITE_DATA_BEATS_ID_15 = 79, 832 AXI0_WRITE_DATA_BEATS_TOTAL = 80, 833 AXI1_WRITE_DATA_BEATS_TOTAL = 81, 834 AXI2_WRITE_DATA_BEATS_TOTAL = 82, 835 AXI3_WRITE_DATA_BEATS_TOTAL = 83, 836 AXI_WRITE_DATA_BEATS_TOTAL = 84, 837 AXI_DATA_BEATS_TOTAL = 85, 838 }; 839 840 enum a5xx_tex_filter { 841 A5XX_TEX_NEAREST = 0, 842 A5XX_TEX_LINEAR = 1, 843 A5XX_TEX_ANISO = 2, 844 }; 845 846 enum a5xx_tex_clamp { 847 A5XX_TEX_REPEAT = 0, 848 A5XX_TEX_CLAMP_TO_EDGE = 1, 849 A5XX_TEX_MIRROR_REPEAT = 2, 850 A5XX_TEX_CLAMP_TO_BORDER = 3, 851 A5XX_TEX_MIRROR_CLAMP = 4, 852 }; 853 854 enum a5xx_tex_aniso { 855 A5XX_TEX_ANISO_1 = 0, 856 A5XX_TEX_ANISO_2 = 1, 857 A5XX_TEX_ANISO_4 = 2, 858 A5XX_TEX_ANISO_8 = 3, 859 A5XX_TEX_ANISO_16 = 4, 860 }; 861 862 enum a5xx_tex_swiz { 863 A5XX_TEX_X = 0, 864 A5XX_TEX_Y = 1, 865 A5XX_TEX_Z = 2, 866 A5XX_TEX_W = 3, 867 A5XX_TEX_ZERO = 4, 868 A5XX_TEX_ONE = 5, 869 }; 870 871 enum a5xx_tex_type { 872 A5XX_TEX_1D = 0, 873 A5XX_TEX_2D = 1, 874 A5XX_TEX_CUBE = 2, 875 A5XX_TEX_3D = 3, 876 }; 877 878 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 879 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 880 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 881 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 882 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 883 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 884 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 885 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 886 #define A5XX_INT0_CP_SW 0x00000100 887 #define A5XX_INT0_CP_HW_ERROR 0x00000200 888 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 889 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 890 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 891 #define A5XX_INT0_CP_IB2 0x00002000 892 #define A5XX_INT0_CP_IB1 0x00004000 893 #define A5XX_INT0_CP_RB 0x00008000 894 #define A5XX_INT0_CP_UNUSED_1 0x00010000 895 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000 896 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000 897 #define A5XX_INT0_UNKNOWN_1 0x00080000 898 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 899 #define A5XX_INT0_UNUSED_2 0x00200000 900 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 901 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000 902 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 903 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 904 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000 905 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000 906 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 907 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000 908 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 909 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 910 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 911 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 912 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 913 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 914 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 915 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 916 #define REG_A5XX_CP_RB_BASE 0x00000800 917 918 #define REG_A5XX_CP_RB_BASE_HI 0x00000801 919 920 #define REG_A5XX_CP_RB_CNTL 0x00000802 921 922 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 923 924 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 925 926 #define REG_A5XX_CP_RB_RPTR 0x00000806 927 928 #define REG_A5XX_CP_RB_WPTR 0x00000807 929 930 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 931 932 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 933 934 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b 935 936 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c 937 938 #define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d 939 940 #define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e 941 942 #define REG_A5XX_CP_ME_NRT_DATA 0x00000810 943 944 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 945 946 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 947 948 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 949 950 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a 951 952 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f 953 954 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 955 956 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 957 958 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 959 960 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 961 962 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 963 964 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 965 966 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826 967 968 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 969 970 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 971 972 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 973 974 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a 975 976 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b 977 978 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f 979 980 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 981 982 #define REG_A5XX_CP_CNTL 0x00000831 983 984 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 985 986 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833 987 988 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 989 990 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 991 992 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 993 994 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 995 996 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b 997 998 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c 999 1000 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d 1001 1002 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e 1003 1004 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f 1005 1006 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 1007 1008 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 1009 1010 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 1011 1012 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 1013 1014 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 1015 1016 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 1017 1018 #define REG_A5XX_CP_HW_FAULT 0x00000b1a 1019 1020 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c 1021 1022 #define REG_A5XX_CP_IB1_BASE 0x00000b1f 1023 1024 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 1025 1026 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 1027 1028 #define REG_A5XX_CP_IB2_BASE 0x00000b22 1029 1030 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 1031 1032 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 1033 1034 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 1035 1036 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 1037 1038 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } 1039 1040 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } 1041 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 1042 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 1044 { 1045 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; 1046 } 1047 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 1048 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 1050 { 1051 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; 1052 } 1053 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 1054 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 1055 1056 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 1057 1058 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b 1059 1060 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 1061 1062 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 1063 1064 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 1065 1066 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 1067 1068 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 1069 1070 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 1071 1072 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 1073 1074 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 1075 1076 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 1077 1078 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba 1079 1080 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb 1081 1082 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc 1083 1084 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd 1085 1086 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 1087 1088 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 1089 1090 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 1091 1092 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 1093 1094 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 1095 1096 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 1097 1098 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 1099 1100 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a 1101 1102 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b 1103 1104 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c 1105 1106 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d 1107 1108 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e 1109 1110 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f 1111 1112 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 1113 1114 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 1115 1116 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 1117 1118 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 1119 1120 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 1121 1122 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 1123 1124 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 1125 1126 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 1127 1128 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 1129 1130 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 1131 1132 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a 1133 1134 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b 1135 1136 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c 1137 1138 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d 1139 1140 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e 1141 1142 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f 1143 1144 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 1145 1146 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 1147 1148 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 1149 1150 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 1151 1152 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 1153 1154 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f 1155 1156 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 1157 1158 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038 1159 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 1160 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 1161 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 1162 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 1163 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 1164 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 1165 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 1166 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 1167 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 1168 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 1169 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 1170 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 1171 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 1172 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 1173 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 1174 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1175 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 1176 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 1177 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1178 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 1179 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 1180 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 1181 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 1182 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 1183 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1184 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 1185 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 1186 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 1187 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 1188 1189 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f 1190 1191 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 1192 1193 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 1194 1195 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1196 1197 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 1198 1199 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 1200 1201 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 1202 1203 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a 1204 1205 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b 1206 1207 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c 1208 1209 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d 1210 1211 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e 1212 1213 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f 1214 1215 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 1216 1217 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 1218 1219 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 1220 1221 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 1222 1223 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 1224 1225 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 1226 1227 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 1228 1229 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a 1230 1231 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b 1232 1233 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c 1234 1235 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d 1236 1237 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e 1238 1239 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f 1240 1241 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 1242 1243 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 1244 1245 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 1246 1247 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 1248 1249 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 1250 1251 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 1252 1253 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 1254 1255 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 1256 1257 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 1258 1259 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 1260 1261 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a 1262 1263 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b 1264 1265 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c 1266 1267 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d 1268 1269 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e 1270 1271 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f 1272 1273 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 1274 1275 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 1276 1277 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 1278 1279 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 1280 1281 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 1282 1283 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 1284 1285 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 1286 1287 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 1288 1289 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 1290 1291 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 1292 1293 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a 1294 1295 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b 1296 1297 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c 1298 1299 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d 1300 1301 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e 1302 1303 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f 1304 1305 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 1306 1307 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 1308 1309 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 1310 1311 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 1312 1313 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 1314 1315 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 1316 1317 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 1318 1319 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 1320 1321 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 1322 1323 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 1324 1325 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a 1326 1327 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b 1328 1329 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c 1330 1331 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d 1332 1333 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e 1334 1335 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f 1336 1337 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 1338 1339 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 1340 1341 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 1342 1343 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 1344 1345 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 1346 1347 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 1348 1349 #define REG_A5XX_RBBM_AHB_CMD 0x00000096 1350 1351 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c 1352 1353 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d 1354 1355 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e 1356 1357 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f 1358 1359 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 1360 1361 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 1362 1363 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 1364 1365 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 1366 1367 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 1368 1369 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 1370 1371 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 1372 1373 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 1374 1375 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 1376 1377 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 1378 1379 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa 1380 1381 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab 1382 1383 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac 1384 1385 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad 1386 1387 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae 1388 1389 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af 1390 1391 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 1392 1393 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 1394 1395 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 1396 1397 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 1398 1399 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 1400 1401 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 1402 1403 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 1404 1405 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 1406 1407 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 1408 1409 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 1410 1411 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba 1412 1413 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb 1414 1415 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 1416 1417 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 1418 1419 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca 1420 1421 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 1422 1423 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 1424 1425 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 1426 1427 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 1428 1429 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 1430 1431 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 1432 1433 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 1434 1435 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 1436 1437 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 1438 1439 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 1440 1441 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa 1442 1443 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab 1444 1445 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac 1446 1447 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad 1448 1449 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae 1450 1451 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af 1452 1453 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 1454 1455 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 1456 1457 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 1458 1459 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 1460 1461 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 1462 1463 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 1464 1465 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 1466 1467 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 1468 1469 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 1470 1471 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 1472 1473 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba 1474 1475 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb 1476 1477 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc 1478 1479 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd 1480 1481 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be 1482 1483 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf 1484 1485 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 1486 1487 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 1488 1489 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 1490 1491 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 1492 1493 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 1494 1495 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 1496 1497 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 1498 1499 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 1500 1501 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 1502 1503 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 1504 1505 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca 1506 1507 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb 1508 1509 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc 1510 1511 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd 1512 1513 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce 1514 1515 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf 1516 1517 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 1518 1519 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 1520 1521 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 1522 1523 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 1524 1525 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 1526 1527 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 1528 1529 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 1530 1531 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 1532 1533 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 1534 1535 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 1536 1537 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da 1538 1539 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db 1540 1541 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc 1542 1543 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd 1544 1545 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de 1546 1547 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df 1548 1549 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 1550 1551 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 1552 1553 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 1554 1555 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 1556 1557 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 1558 1559 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 1560 1561 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 1562 1563 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 1564 1565 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 1566 1567 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 1568 1569 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea 1570 1571 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb 1572 1573 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec 1574 1575 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed 1576 1577 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee 1578 1579 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef 1580 1581 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 1582 1583 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 1584 1585 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 1586 1587 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 1588 1589 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 1590 1591 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 1592 1593 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 1594 1595 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 1596 1597 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 1598 1599 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 1600 1601 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa 1602 1603 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb 1604 1605 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc 1606 1607 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd 1608 1609 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe 1610 1611 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff 1612 1613 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 1614 1615 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 1616 1617 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 1618 1619 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 1620 1621 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 1622 1623 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 1624 1625 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 1626 1627 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 1628 1629 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 1630 1631 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 1632 1633 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a 1634 1635 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b 1636 1637 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c 1638 1639 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d 1640 1641 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e 1642 1643 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f 1644 1645 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 1646 1647 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 1648 1649 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 1650 1651 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 1652 1653 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 1654 1655 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 1656 1657 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 1658 1659 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 1660 1661 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 1662 1663 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 1664 1665 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a 1666 1667 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b 1668 1669 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c 1670 1671 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d 1672 1673 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e 1674 1675 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f 1676 1677 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 1678 1679 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 1680 1681 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 1682 1683 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 1684 1685 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 1686 1687 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 1688 1689 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 1690 1691 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 1692 1693 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 1694 1695 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 1696 1697 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a 1698 1699 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b 1700 1701 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c 1702 1703 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d 1704 1705 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e 1706 1707 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f 1708 1709 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 1710 1711 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 1712 1713 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 1714 1715 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 1716 1717 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 1718 1719 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 1720 1721 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 1722 1723 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 1724 1725 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 1726 1727 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 1728 1729 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a 1730 1731 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b 1732 1733 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c 1734 1735 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d 1736 1737 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e 1738 1739 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f 1740 1741 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 1742 1743 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 1744 1745 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 1746 1747 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 1748 1749 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 1750 1751 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 1752 1753 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 1754 1755 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 1756 1757 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 1758 1759 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 1760 1761 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a 1762 1763 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b 1764 1765 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c 1766 1767 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d 1768 1769 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e 1770 1771 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f 1772 1773 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 1774 1775 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 1776 1777 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 1778 1779 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 1780 1781 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 1782 1783 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 1784 1785 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 1786 1787 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 1788 1789 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 1790 1791 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 1792 1793 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a 1794 1795 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b 1796 1797 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c 1798 1799 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d 1800 1801 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e 1802 1803 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f 1804 1805 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 1806 1807 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 1808 1809 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 1810 1811 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 1812 1813 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1814 1815 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1816 1817 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1818 1819 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1820 1821 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 1822 1823 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 1824 1825 #define REG_A5XX_RBBM_STATUS 0x000004f5 1826 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 1827 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 1828 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 1829 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 1830 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 1831 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 1832 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 1833 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 1834 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 1835 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 1836 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 1837 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 1838 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 1839 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 1840 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 1841 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 1842 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 1843 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 1844 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 1845 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 1846 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 1847 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 1848 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 1849 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 1850 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 1851 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 1852 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 1853 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 1854 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 1855 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 1856 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 1857 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 1858 1859 #define REG_A5XX_RBBM_STATUS3 0x00000530 1860 1861 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 1862 1863 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 1864 1865 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 1866 1867 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 1868 1869 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 1870 1871 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 1872 1873 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 1874 1875 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 1876 1877 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 1878 1879 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 1880 1881 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 1882 1883 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a 1884 1885 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1886 1887 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1888 1889 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1890 1891 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1892 1893 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f 1894 1895 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed 1896 1897 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 1898 1899 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 1900 1901 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 1902 1903 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 1904 1905 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 1906 1907 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 1908 1909 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a 1910 1911 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b 1912 1913 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c 1914 1915 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d 1916 1917 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e 1918 1919 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f 1920 1921 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 1922 1923 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 1924 1925 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 1926 1927 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 1928 1929 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533 1930 1931 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 1932 1933 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 1934 1935 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 1936 1937 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 1938 1939 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 1940 1941 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 1942 1943 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 1944 1945 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 1946 1947 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 1948 1949 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 1950 1951 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 1952 1953 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2 1954 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 1955 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1956 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1957 { 1958 assert(!(val & 0x1f)); 1959 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; 1960 } 1961 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00 1962 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9 1963 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1964 { 1965 assert(!(val & 0x1f)); 1966 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; 1967 } 1968 1969 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3 1970 1971 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4 1972 1973 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5 1974 1975 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6 1976 1977 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } 1978 1979 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } 1980 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1981 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1982 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1983 { 1984 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; 1985 } 1986 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1987 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1988 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1989 { 1990 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1991 } 1992 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1993 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1994 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1995 { 1996 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK; 1997 } 1998 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1999 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 2000 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2001 { 2002 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK; 2003 } 2004 2005 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } 2006 2007 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } 2008 2009 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } 2010 2011 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } 2012 2013 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } 2014 2015 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 2016 2017 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 2018 2019 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd 2020 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000 2021 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff 2022 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0 2023 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) 2024 { 2025 return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK; 2026 } 2027 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000 2028 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16 2029 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 2030 { 2031 return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK; 2032 } 2033 2034 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 2035 2036 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 2037 2038 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 2039 2040 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 2041 2042 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 2043 2044 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 2045 2046 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 2047 2048 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 2049 2050 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 2051 2052 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 2053 2054 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 2055 2056 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a 2057 2058 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b 2059 2060 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 2061 2062 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 2063 2064 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6 2065 2066 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7 2067 2068 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 2069 2070 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 2071 2072 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 2073 2074 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 2075 2076 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 2077 2078 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 2079 2080 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 2081 2082 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 2083 2084 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 2085 2086 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 2087 2088 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda 2089 2090 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb 2091 2092 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 2093 2094 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 2095 2096 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 2097 2098 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 2099 2100 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 2101 2102 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 2103 2104 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec 2105 2106 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced 2107 2108 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee 2109 2110 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef 2111 2112 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 2113 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 2114 2115 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 2116 2117 #define REG_A5XX_PC_MODE_CNTL 0x00000d02 2118 2119 #define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04 2120 2121 #define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05 2122 2123 #define REG_A5XX_PC_START_INDEX 0x00000d06 2124 2125 #define REG_A5XX_PC_MAX_INDEX 0x00000d07 2126 2127 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08 2128 2129 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09 2130 2131 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2132 2133 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 2134 2135 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 2136 2137 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 2138 2139 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 2140 2141 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 2142 2143 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 2144 2145 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2146 2147 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 2148 2149 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 2150 2151 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 2152 2153 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 2154 2155 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 2156 2157 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 2158 2159 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 2160 2161 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 2162 2163 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 2164 2165 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 2166 2167 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 2168 2169 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 2170 2171 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 2172 2173 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 2174 2175 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 2176 2177 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 2178 2179 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42 2180 2181 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 2182 2183 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 2184 2185 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 2186 2187 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 2188 2189 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 2190 2191 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 2192 2193 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 2194 2195 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 2196 2197 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 2198 2199 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 2200 2201 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62 2202 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001 2203 2204 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 2205 2206 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 2207 2208 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 2209 2210 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 2211 2212 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 2213 2214 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 2215 2216 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 2217 2218 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 2219 2220 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 2221 2222 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a 2223 2224 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b 2225 2226 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c 2227 2228 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d 2229 2230 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e 2231 2232 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f 2233 2234 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 2235 2236 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 2237 2238 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 2239 2240 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 2241 2242 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 2243 2244 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 2245 2246 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 2247 2248 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 2249 2250 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 2251 2252 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 2253 2254 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 2255 2256 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 2257 2258 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 2259 2260 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 2261 2262 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 2263 2264 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 2265 2266 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 2267 2268 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa 2269 2270 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab 2271 2272 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 2273 2274 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 2275 2276 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 2277 2278 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 2279 2280 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2 2281 2282 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 2283 2284 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 2285 2286 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 2287 2288 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 2289 2290 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 2291 2292 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 2293 2294 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 2295 2296 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 2297 2298 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 2299 2300 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 2301 2302 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda 2303 2304 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb 2305 2306 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc 2307 2308 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd 2309 2310 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede 2311 2312 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf 2313 2314 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 2315 2316 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 2317 2318 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 2319 2320 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 2321 2322 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 2323 2324 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 2325 2326 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 2327 2328 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 2329 2330 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 2331 2332 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 2333 2334 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 2335 2336 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 2337 2338 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a 2339 2340 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b 2341 2342 #define REG_A5XX_VBIF_VERSION 0x00003000 2343 2344 #define REG_A5XX_VBIF_CLKON 0x00003001 2345 2346 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028 2347 2348 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 2349 2350 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2351 2352 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2353 2354 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2355 2356 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2357 2358 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 2359 2360 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 2361 2362 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2363 2364 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2365 2366 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2367 2368 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2369 2370 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2371 2372 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c 2373 2374 #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0 2375 2376 #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1 2377 2378 #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2 2379 2380 #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3 2381 2382 #define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8 2383 2384 #define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c8 2385 2386 #define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030c8 2387 2388 #define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030c8 2389 2390 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0 2391 2392 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1 2393 2394 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2 2395 2396 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3 2397 2398 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 2399 2400 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 2401 2402 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da 2403 2404 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db 2405 2406 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 2407 2408 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 2409 2410 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 2411 2412 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 2413 2414 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 2415 2416 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 2417 2418 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 2419 2420 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 2421 2422 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 2423 2424 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 2425 2426 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 2427 2428 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 2429 2430 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 2431 2432 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 2433 2434 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 2435 2436 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 2437 2438 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 2439 2440 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 2441 2442 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b 2443 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 2444 2445 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d 2446 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 2447 2448 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 2449 2450 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 2451 2452 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 2453 2454 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 2455 2456 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 2457 2458 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 2459 2460 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 2461 2462 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 2463 2464 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 2465 2466 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 2467 2468 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 2469 2470 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 2471 2472 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 2473 2474 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 2475 2476 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 2477 2478 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 2479 2480 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 2481 2482 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 2483 2484 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 2485 2486 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 2487 2488 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a 2489 2490 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b 2491 2492 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c 2493 2494 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d 2495 2496 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e 2497 2498 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f 2499 2500 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 2501 2502 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 2503 2504 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 2505 2506 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 2507 2508 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 2509 2510 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 2511 2512 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 2513 2514 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 2515 2516 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 2517 2518 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 2519 2520 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a 2521 2522 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b 2523 2524 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c 2525 2526 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d 2527 2528 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e 2529 2530 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f 2531 2532 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 2533 2534 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 2535 2536 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 2537 2538 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 2539 2540 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 2541 2542 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 2543 2544 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 2545 2546 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 2547 2548 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 2549 2550 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 2551 2552 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a 2553 2554 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b 2555 2556 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c 2557 2558 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d 2559 2560 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e 2561 2562 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f 2563 2564 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 2565 2566 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 2567 2568 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 2569 2570 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 2571 2572 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 2573 2574 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 2575 2576 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 2577 2578 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 2579 2580 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 2581 2582 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 2583 2584 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a 2585 2586 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b 2587 2588 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c 2589 2590 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d 2591 2592 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 2593 2594 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 2595 2596 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 2597 2598 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 2599 2600 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 2601 2602 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 2603 2604 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 2605 2606 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 2607 2608 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 2609 2610 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 2611 2612 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 2613 2614 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 2615 2616 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 2617 2618 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 2619 2620 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 2621 2622 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 2623 2624 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 2625 2626 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 2627 2628 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 2629 2630 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c 2631 2632 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d 2633 2634 #define REG_A5XX_GDPM_INT_EN 0x0000b80f 2635 2636 #define REG_A5XX_GDPM_INT_MASK 0x0000b811 2637 2638 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 2639 2640 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a 2641 2642 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d 2643 2644 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f 2645 2646 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 2647 2648 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 2649 2650 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 2651 2652 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000 2653 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2654 2655 #define REG_A5XX_UNKNOWN_E001 0x0000e001 2656 2657 #define REG_A5XX_UNKNOWN_E004 0x0000e004 2658 2659 #define REG_A5XX_GRAS_CNTL 0x0000e005 2660 #define A5XX_GRAS_CNTL_VARYING 0x00000001 2661 #define A5XX_GRAS_CNTL_UNK3 0x00000008 2662 #define A5XX_GRAS_CNTL_XCOORD 0x00000040 2663 #define A5XX_GRAS_CNTL_YCOORD 0x00000080 2664 #define A5XX_GRAS_CNTL_ZCOORD 0x00000100 2665 #define A5XX_GRAS_CNTL_WCOORD 0x00000200 2666 2667 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 2668 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 2669 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 2670 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 2671 { 2672 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 2673 } 2674 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 2675 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 2676 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 2677 { 2678 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 2679 } 2680 2681 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 2682 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2683 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2684 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2685 { 2686 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2687 } 2688 2689 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 2690 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2691 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2692 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) 2693 { 2694 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2695 } 2696 2697 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 2698 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2699 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2700 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2701 { 2702 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2703 } 2704 2705 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 2706 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2707 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2708 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) 2709 { 2710 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2711 } 2712 2713 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 2714 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2715 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2716 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2717 { 2718 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2719 } 2720 2721 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 2722 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2723 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2724 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2725 { 2726 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2727 } 2728 2729 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090 2730 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 2731 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 2732 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 2733 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 2734 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 2735 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 2736 { 2737 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 2738 } 2739 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2740 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 2741 2742 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 2743 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2744 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2745 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2746 { 2747 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2748 } 2749 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2750 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2751 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2752 { 2753 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2754 } 2755 2756 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 2757 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2758 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 2759 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) 2760 { 2761 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; 2762 } 2763 2764 #define REG_A5XX_GRAS_SU_LAYERED 0x0000e093 2765 2766 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 2767 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 2768 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002 2769 2770 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 2771 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2772 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2773 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2774 { 2775 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2776 } 2777 2778 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 2779 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2780 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2781 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2782 { 2783 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2784 } 2785 2786 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 2787 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2788 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2789 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2790 { 2791 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2792 } 2793 2794 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 2795 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2796 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2797 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 2798 { 2799 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2800 } 2801 2802 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 2803 2804 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 2805 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001 2806 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000 2807 2808 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 2809 2810 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 2811 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2812 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2813 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2814 { 2815 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; 2816 } 2817 2818 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 2819 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2820 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2821 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2822 { 2823 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; 2824 } 2825 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2826 2827 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 2828 2829 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa 2830 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2831 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 2832 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 2833 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 2834 { 2835 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 2836 } 2837 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 2838 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 2839 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 2840 { 2841 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 2842 } 2843 2844 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab 2845 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2846 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 2847 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 2848 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 2849 { 2850 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 2851 } 2852 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 2853 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 2854 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 2855 { 2856 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 2857 } 2858 2859 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca 2860 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2861 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 2862 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 2863 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 2864 { 2865 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 2866 } 2867 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 2868 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 2869 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 2870 { 2871 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 2872 } 2873 2874 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb 2875 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2876 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 2877 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 2878 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 2879 { 2880 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 2881 } 2882 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 2883 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 2884 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 2885 { 2886 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 2887 } 2888 2889 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea 2890 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2891 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2892 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2893 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2894 { 2895 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2896 } 2897 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2898 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2899 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2900 { 2901 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2902 } 2903 2904 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb 2905 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2906 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2907 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2908 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2909 { 2910 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2911 } 2912 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2913 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2914 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2915 { 2916 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2917 } 2918 2919 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 2920 #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 2921 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 2922 #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2923 2924 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 2925 2926 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 2927 2928 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 2929 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff 2930 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0 2931 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) 2932 { 2933 assert(!(val & 0x1f)); 2934 return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; 2935 } 2936 2937 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 2938 2939 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 2940 2941 #define REG_A5XX_RB_CNTL 0x0000e140 2942 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff 2943 #define A5XX_RB_CNTL_WIDTH__SHIFT 0 2944 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) 2945 { 2946 assert(!(val & 0x1f)); 2947 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; 2948 } 2949 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 2950 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9 2951 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) 2952 { 2953 assert(!(val & 0x1f)); 2954 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; 2955 } 2956 #define A5XX_RB_CNTL_BYPASS 0x00020000 2957 2958 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141 2959 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001 2960 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040 2961 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080 2962 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2963 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000 2964 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2965 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2966 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2967 { 2968 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2969 } 2970 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000 2971 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24 2972 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) 2973 { 2974 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; 2975 } 2976 2977 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 2978 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2979 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2980 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2981 { 2982 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 2983 } 2984 2985 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 2986 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2987 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2988 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2989 { 2990 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 2991 } 2992 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2993 2994 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 2995 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 2996 #define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008 2997 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 2998 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 2999 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 3000 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 3001 3002 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 3003 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 3004 3005 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 3006 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 3007 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 3008 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) 3009 { 3010 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; 3011 } 3012 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 3013 3014 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147 3015 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 3016 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 3017 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 3018 { 3019 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; 3020 } 3021 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 3022 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 3023 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 3024 { 3025 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; 3026 } 3027 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 3028 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 3029 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 3030 { 3031 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; 3032 } 3033 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 3034 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 3035 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 3036 { 3037 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; 3038 } 3039 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 3040 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 3041 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 3042 { 3043 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; 3044 } 3045 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 3046 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 3047 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 3048 { 3049 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; 3050 } 3051 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 3052 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 3053 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 3054 { 3055 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; 3056 } 3057 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 3058 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 3059 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 3060 { 3061 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; 3062 } 3063 3064 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 3065 3066 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 3067 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 3068 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 3069 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 3070 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 3071 #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 3072 static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 3073 { 3074 return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK; 3075 } 3076 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 3077 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 3078 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 3079 { 3080 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 3081 } 3082 3083 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } 3084 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 3085 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 3086 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 3087 { 3088 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 3089 } 3090 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 3091 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 3092 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3093 { 3094 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 3095 } 3096 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 3097 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 3098 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 3099 { 3100 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 3101 } 3102 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 3103 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 3104 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 3105 { 3106 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 3107 } 3108 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 3109 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 3110 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3111 { 3112 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 3113 } 3114 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 3115 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 3116 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 3117 { 3118 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 3119 } 3120 3121 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } 3122 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 3123 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3124 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3125 { 3126 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 3127 } 3128 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 3129 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 3130 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) 3131 { 3132 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 3133 } 3134 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 3135 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 3136 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3137 { 3138 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 3139 } 3140 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 3141 3142 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } 3143 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff 3144 #define A5XX_RB_MRT_PITCH__SHIFT 0 3145 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) 3146 { 3147 assert(!(val & 0x3f)); 3148 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; 3149 } 3150 3151 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } 3152 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 3153 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 3154 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) 3155 { 3156 assert(!(val & 0x3f)); 3157 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; 3158 } 3159 3160 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } 3161 3162 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } 3163 3164 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0 3165 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff 3166 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0 3167 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) 3168 { 3169 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; 3170 } 3171 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 3172 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8 3173 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) 3174 { 3175 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; 3176 } 3177 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 3178 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 3179 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) 3180 { 3181 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; 3182 } 3183 3184 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 3185 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff 3186 #define A5XX_RB_BLEND_RED_F32__SHIFT 0 3187 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) 3188 { 3189 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; 3190 } 3191 3192 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 3193 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 3194 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 3195 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) 3196 { 3197 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; 3198 } 3199 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 3200 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 3201 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) 3202 { 3203 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; 3204 } 3205 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 3206 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 3207 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) 3208 { 3209 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; 3210 } 3211 3212 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 3213 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 3214 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 3215 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) 3216 { 3217 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; 3218 } 3219 3220 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 3221 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 3222 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 3223 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) 3224 { 3225 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; 3226 } 3227 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 3228 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 3229 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) 3230 { 3231 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; 3232 } 3233 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 3234 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 3235 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) 3236 { 3237 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; 3238 } 3239 3240 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 3241 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 3242 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 3243 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) 3244 { 3245 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; 3246 } 3247 3248 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 3249 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 3250 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 3251 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) 3252 { 3253 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; 3254 } 3255 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 3256 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 3257 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) 3258 { 3259 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; 3260 } 3261 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 3262 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 3263 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) 3264 { 3265 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; 3266 } 3267 3268 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 3269 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 3270 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 3271 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) 3272 { 3273 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; 3274 } 3275 3276 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 3277 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 3278 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 3279 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 3280 { 3281 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 3282 } 3283 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 3284 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 3285 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 3286 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 3287 { 3288 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 3289 } 3290 3291 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 3292 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 3293 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 3294 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 3295 { 3296 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 3297 } 3298 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3299 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 3300 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 3301 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 3302 { 3303 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 3304 } 3305 3306 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 3307 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 3308 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002 3309 3310 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 3311 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 3312 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 3313 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 3314 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 3315 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 3316 { 3317 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; 3318 } 3319 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 3320 3321 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 3322 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 3323 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 3324 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 3325 { 3326 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 3327 } 3328 3329 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 3330 3331 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 3332 3333 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 3334 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 3335 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 3336 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 3337 { 3338 assert(!(val & 0x3f)); 3339 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; 3340 } 3341 3342 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 3343 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3344 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 3345 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 3346 { 3347 assert(!(val & 0x3f)); 3348 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 3349 } 3350 3351 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 3352 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 3353 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 3354 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 3355 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 3356 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 3357 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 3358 { 3359 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; 3360 } 3361 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 3362 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 3363 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 3364 { 3365 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; 3366 } 3367 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 3368 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 3369 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 3370 { 3371 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; 3372 } 3373 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 3374 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 3375 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 3376 { 3377 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 3378 } 3379 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 3380 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 3381 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 3382 { 3383 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 3384 } 3385 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 3386 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 3387 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 3388 { 3389 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 3390 } 3391 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 3392 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 3393 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 3394 { 3395 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 3396 } 3397 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 3398 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 3399 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 3400 { 3401 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 3402 } 3403 3404 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1 3405 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3406 3407 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2 3408 3409 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3 3410 3411 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4 3412 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff 3413 #define A5XX_RB_STENCIL_PITCH__SHIFT 0 3414 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) 3415 { 3416 assert(!(val & 0x3f)); 3417 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; 3418 } 3419 3420 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 3421 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff 3422 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 3423 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) 3424 { 3425 assert(!(val & 0x3f)); 3426 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; 3427 } 3428 3429 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 3430 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 3431 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 3432 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 3433 { 3434 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; 3435 } 3436 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 3437 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 3438 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 3439 { 3440 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; 3441 } 3442 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 3443 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 3444 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 3445 { 3446 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 3447 } 3448 3449 #define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7 3450 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 3451 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 3452 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 3453 { 3454 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 3455 } 3456 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 3457 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 3458 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 3459 { 3460 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 3461 } 3462 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 3463 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 3464 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 3465 { 3466 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 3467 } 3468 3469 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 3470 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 3471 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 3472 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 3473 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) 3474 { 3475 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; 3476 } 3477 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 3478 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 3479 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) 3480 { 3481 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; 3482 } 3483 3484 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1 3485 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 3486 3487 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210 3488 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f 3489 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0 3490 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) 3491 { 3492 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; 3493 } 3494 3495 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 3496 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 3497 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff 3498 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 3499 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) 3500 { 3501 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; 3502 } 3503 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 3504 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 3505 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) 3506 { 3507 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; 3508 } 3509 3510 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 3511 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 3512 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff 3513 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 3514 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) 3515 { 3516 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; 3517 } 3518 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 3519 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 3520 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) 3521 { 3522 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; 3523 } 3524 3525 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213 3526 #define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001 3527 3528 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214 3529 3530 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215 3531 3532 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216 3533 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 3534 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 3535 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) 3536 { 3537 assert(!(val & 0x3f)); 3538 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; 3539 } 3540 3541 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 3542 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 3543 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 3544 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 3545 { 3546 assert(!(val & 0x3f)); 3547 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 3548 } 3549 3550 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 3551 3552 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219 3553 3554 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a 3555 3556 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b 3557 3558 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c 3559 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002 3560 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0 3561 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4 3562 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) 3563 { 3564 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; 3565 } 3566 3567 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 3568 3569 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 3570 3571 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 3572 3573 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 3574 3575 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 3576 3577 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } 3578 3579 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } 3580 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff 3581 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 3582 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) 3583 { 3584 assert(!(val & 0x3f)); 3585 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; 3586 } 3587 3588 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } 3589 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3590 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 3591 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 3592 { 3593 assert(!(val & 0x3f)); 3594 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; 3595 } 3596 3597 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 3598 3599 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264 3600 3601 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265 3602 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff 3603 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 3604 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) 3605 { 3606 assert(!(val & 0x3f)); 3607 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; 3608 } 3609 3610 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 3611 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff 3612 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 3613 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) 3614 { 3615 assert(!(val & 0x3f)); 3616 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; 3617 } 3618 3619 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267 3620 3621 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268 3622 3623 #define REG_A5XX_VPC_CNTL_0 0x0000e280 3624 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f 3625 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 3626 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) 3627 { 3628 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; 3629 } 3630 #define A5XX_VPC_CNTL_0_VARYING 0x00000800 3631 3632 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 3633 3634 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 3635 3636 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 3637 3638 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 3639 3640 #define REG_A5XX_UNKNOWN_E292 0x0000e292 3641 3642 #define REG_A5XX_UNKNOWN_E293 0x0000e293 3643 3644 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 3645 3646 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 3647 3648 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 3649 3650 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a 3651 3652 #define REG_A5XX_VPC_PACK 0x0000e29d 3653 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff 3654 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 3655 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 3656 { 3657 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; 3658 } 3659 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00 3660 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8 3661 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) 3662 { 3663 return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK; 3664 } 3665 3666 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 3667 3668 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1 3669 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 3670 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 3671 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 3672 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 3673 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 3674 3675 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 3676 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 3677 3678 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3 3679 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000 3680 3681 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4 3682 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 3683 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0 3684 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) 3685 { 3686 return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK; 3687 } 3688 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 3689 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2 3690 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) 3691 { 3692 assert(!(val & 0x3)); 3693 return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; 3694 } 3695 #define A5XX_VPC_SO_PROG_A_EN 0x00000800 3696 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 3697 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12 3698 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) 3699 { 3700 return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK; 3701 } 3702 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 3703 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14 3704 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) 3705 { 3706 assert(!(val & 0x3)); 3707 return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; 3708 } 3709 #define A5XX_VPC_SO_PROG_B_EN 0x00800000 3710 3711 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } 3712 3713 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } 3714 3715 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; } 3716 3717 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; } 3718 3719 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; } 3720 3721 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; } 3722 3723 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; } 3724 3725 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; } 3726 3727 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 3728 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f 3729 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 3730 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) 3731 { 3732 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; 3733 } 3734 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100 3735 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200 3736 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400 3737 3738 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385 3739 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800 3740 3741 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388 3742 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007 3743 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0 3744 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 3745 { 3746 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK; 3747 } 3748 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038 3749 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3 3750 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 3751 { 3752 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK; 3753 } 3754 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040 3755 3756 #define REG_A5XX_UNKNOWN_E389 0x0000e389 3757 3758 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c 3759 3760 #define REG_A5XX_PC_GS_LAYERED 0x0000e38d 3761 3762 #define REG_A5XX_PC_GS_PARAM 0x0000e38e 3763 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 3764 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 3765 static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 3766 { 3767 return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK; 3768 } 3769 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 3770 #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 3771 static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 3772 { 3773 return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK; 3774 } 3775 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 3776 #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 3777 static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3778 { 3779 return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK; 3780 } 3781 3782 #define REG_A5XX_PC_HS_PARAM 0x0000e38f 3783 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 3784 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 3785 static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 3786 { 3787 return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK; 3788 } 3789 #define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000 3790 #define A5XX_PC_HS_PARAM_SPACING__SHIFT 21 3791 static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 3792 { 3793 return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK; 3794 } 3795 #define A5XX_PC_HS_PARAM_CW 0x00800000 3796 #define A5XX_PC_HS_PARAM_CONNECTED 0x01000000 3797 3798 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 3799 3800 #define REG_A5XX_VFD_CONTROL_0 0x0000e400 3801 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 3802 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 3803 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 3804 { 3805 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; 3806 } 3807 3808 #define REG_A5XX_VFD_CONTROL_1 0x0000e401 3809 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 3810 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 3811 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 3812 { 3813 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; 3814 } 3815 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 3816 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 3817 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 3818 { 3819 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; 3820 } 3821 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 3822 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 3823 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 3824 { 3825 return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 3826 } 3827 3828 #define REG_A5XX_VFD_CONTROL_2 0x0000e402 3829 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff 3830 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0 3831 static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) 3832 { 3833 return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK; 3834 } 3835 3836 #define REG_A5XX_VFD_CONTROL_3 0x0000e403 3837 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00 3838 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8 3839 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) 3840 { 3841 return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK; 3842 } 3843 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 3844 #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 3845 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 3846 { 3847 return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK; 3848 } 3849 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 3850 #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 3851 static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 3852 { 3853 return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK; 3854 } 3855 3856 #define REG_A5XX_VFD_CONTROL_4 0x0000e404 3857 3858 #define REG_A5XX_VFD_CONTROL_5 0x0000e405 3859 3860 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 3861 3862 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 3863 3864 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 3865 3866 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 3867 3868 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } 3869 3870 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } 3871 3872 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } 3873 3874 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 3875 3876 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 3877 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 3878 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 3879 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) 3880 { 3881 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; 3882 } 3883 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 3884 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 3885 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 3886 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) 3887 { 3888 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; 3889 } 3890 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 3891 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 3892 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 3893 { 3894 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK; 3895 } 3896 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000 3897 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000 3898 3899 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } 3900 3901 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 3902 3903 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 3904 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 3905 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 3906 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 3907 { 3908 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 3909 } 3910 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 3911 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 3912 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 3913 { 3914 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 3915 } 3916 3917 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 3918 3919 #define REG_A5XX_SP_SP_CNTL 0x0000e580 3920 3921 #define REG_A5XX_SP_VS_CONFIG 0x0000e584 3922 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001 3923 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3924 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3925 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3926 { 3927 return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK; 3928 } 3929 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3930 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3931 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3932 { 3933 return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK; 3934 } 3935 3936 #define REG_A5XX_SP_FS_CONFIG 0x0000e585 3937 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001 3938 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3939 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3940 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3941 { 3942 return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK; 3943 } 3944 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3945 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3946 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3947 { 3948 return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK; 3949 } 3950 3951 #define REG_A5XX_SP_HS_CONFIG 0x0000e586 3952 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001 3953 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3954 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3955 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3956 { 3957 return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK; 3958 } 3959 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3960 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3961 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3962 { 3963 return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK; 3964 } 3965 3966 #define REG_A5XX_SP_DS_CONFIG 0x0000e587 3967 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001 3968 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3969 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3970 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3971 { 3972 return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK; 3973 } 3974 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3975 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3976 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3977 { 3978 return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK; 3979 } 3980 3981 #define REG_A5XX_SP_GS_CONFIG 0x0000e588 3982 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001 3983 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3984 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3985 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3986 { 3987 return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK; 3988 } 3989 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3990 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3991 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3992 { 3993 return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK; 3994 } 3995 3996 #define REG_A5XX_SP_CS_CONFIG 0x0000e589 3997 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001 3998 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3999 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4000 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4001 { 4002 return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK; 4003 } 4004 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4005 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4006 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4007 { 4008 return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK; 4009 } 4010 4011 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a 4012 4013 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b 4014 4015 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 4016 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008 4017 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3 4018 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4019 { 4020 return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 4021 } 4022 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 4023 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 4024 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4025 { 4026 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4027 } 4028 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 4029 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 4030 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4031 { 4032 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4033 } 4034 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 4035 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 4036 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 4037 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25 4038 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4039 { 4040 return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 4041 } 4042 4043 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592 4044 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f 4045 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 4046 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) 4047 { 4048 return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; 4049 } 4050 4051 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 4052 4053 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 4054 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 4055 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 4056 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 4057 { 4058 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; 4059 } 4060 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 4061 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 4062 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 4063 { 4064 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 4065 } 4066 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 4067 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 4068 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 4069 { 4070 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; 4071 } 4072 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 4073 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 4074 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 4075 { 4076 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 4077 } 4078 4079 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 4080 4081 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 4082 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 4083 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 4084 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 4085 { 4086 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 4087 } 4088 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 4089 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 4090 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 4091 { 4092 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 4093 } 4094 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 4095 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 4096 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 4097 { 4098 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 4099 } 4100 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 4101 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 4102 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 4103 { 4104 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 4105 } 4106 4107 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab 4108 4109 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac 4110 4111 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad 4112 4113 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 4114 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008 4115 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3 4116 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4117 { 4118 return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 4119 } 4120 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 4121 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 4122 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4123 { 4124 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4125 } 4126 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 4127 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 4128 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4129 { 4130 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4131 } 4132 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 4133 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 4134 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 4135 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25 4136 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4137 { 4138 return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 4139 } 4140 4141 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2 4142 4143 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 4144 4145 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 4146 4147 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 4148 #define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001 4149 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100 4150 4151 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca 4152 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 4153 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 4154 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) 4155 { 4156 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; 4157 } 4158 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 4159 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 4160 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) 4161 { 4162 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; 4163 } 4164 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 4165 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 4166 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) 4167 { 4168 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; 4169 } 4170 4171 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 4172 4173 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 4174 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 4175 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 4176 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 4177 { 4178 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; 4179 } 4180 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 4181 4182 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 4183 4184 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 4185 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 4186 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 4187 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) 4188 { 4189 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 4190 } 4191 #define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 4192 #define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 4193 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400 4194 4195 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db 4196 4197 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0 4198 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008 4199 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3 4200 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4201 { 4202 return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 4203 } 4204 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 4205 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 4206 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4207 { 4208 return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4209 } 4210 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 4211 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 4212 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4213 { 4214 return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4215 } 4216 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000 4217 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000 4218 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 4219 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25 4220 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4221 { 4222 return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 4223 } 4224 4225 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2 4226 4227 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3 4228 4229 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4 4230 4231 #define REG_A5XX_UNKNOWN_E600 0x0000e600 4232 4233 #define REG_A5XX_UNKNOWN_E602 0x0000e602 4234 4235 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603 4236 4237 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604 4238 4239 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b 4240 4241 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c 4242 4243 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d 4244 4245 #define REG_A5XX_UNKNOWN_E640 0x0000e640 4246 4247 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b 4248 4249 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c 4250 4251 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d 4252 4253 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 4254 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 4255 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 4256 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4257 { 4258 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 4259 } 4260 4261 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 4262 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 4263 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 4264 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4265 { 4266 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 4267 } 4268 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 4269 4270 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706 4271 4272 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707 4273 4274 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700 4275 4276 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701 4277 4278 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702 4279 4280 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703 4281 4282 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 4283 4284 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 4285 4286 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724 4287 4288 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725 4289 4290 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726 4291 4292 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727 4293 4294 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728 4295 4296 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729 4297 4298 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a 4299 4300 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b 4301 4302 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c 4303 4304 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d 4305 4306 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e 4307 4308 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f 4309 4310 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730 4311 4312 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731 4313 4314 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750 4315 4316 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751 4317 4318 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a 4319 4320 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b 4321 4322 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c 4323 4324 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d 4325 4326 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e 4327 4328 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f 4329 4330 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760 4331 4332 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761 4333 4334 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 4335 4336 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 4337 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001 4338 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0 4339 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 4340 { 4341 return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 4342 } 4343 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004 4344 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2 4345 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) 4346 { 4347 return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK; 4348 } 4349 4350 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 4351 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f 4352 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 4353 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) 4354 { 4355 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; 4356 } 4357 4358 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 4359 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 4360 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 4361 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 4362 { 4363 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 4364 } 4365 4366 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 4367 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff 4368 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 4369 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) 4370 { 4371 return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; 4372 } 4373 4374 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 4375 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 4376 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 4377 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 4378 { 4379 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 4380 } 4381 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 4382 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 4383 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 4384 { 4385 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 4386 } 4387 4388 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a 4389 4390 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b 4391 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001 4392 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4393 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4394 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4395 { 4396 return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK; 4397 } 4398 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4399 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4400 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4401 { 4402 return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK; 4403 } 4404 4405 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c 4406 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001 4407 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4408 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4409 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4410 { 4411 return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK; 4412 } 4413 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4414 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4415 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4416 { 4417 return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK; 4418 } 4419 4420 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d 4421 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001 4422 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4423 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4424 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4425 { 4426 return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK; 4427 } 4428 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4429 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4430 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4431 { 4432 return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK; 4433 } 4434 4435 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e 4436 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001 4437 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4438 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4439 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4440 { 4441 return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK; 4442 } 4443 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4444 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4445 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4446 { 4447 return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK; 4448 } 4449 4450 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f 4451 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001 4452 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4453 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4454 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4455 { 4456 return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK; 4457 } 4458 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4459 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4460 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4461 { 4462 return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK; 4463 } 4464 4465 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 4466 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001 4467 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4468 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4469 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4470 { 4471 return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK; 4472 } 4473 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4474 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4475 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4476 { 4477 return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK; 4478 } 4479 4480 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 4481 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001 4482 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe 4483 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1 4484 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) 4485 { 4486 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; 4487 } 4488 4489 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 4490 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001 4491 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe 4492 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1 4493 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) 4494 { 4495 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; 4496 } 4497 4498 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793 4499 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001 4500 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe 4501 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1 4502 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) 4503 { 4504 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; 4505 } 4506 4507 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794 4508 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001 4509 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe 4510 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1 4511 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) 4512 { 4513 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; 4514 } 4515 4516 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795 4517 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001 4518 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe 4519 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1 4520 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) 4521 { 4522 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; 4523 } 4524 4525 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 4526 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001 4527 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe 4528 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1 4529 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) 4530 { 4531 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; 4532 } 4533 4534 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 4535 4536 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba 4537 4538 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb 4539 4540 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 4541 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 4542 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 4543 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 4544 { 4545 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 4546 } 4547 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 4548 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 4549 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 4550 { 4551 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 4552 } 4553 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 4554 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 4555 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 4556 { 4557 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 4558 } 4559 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 4560 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 4561 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 4562 { 4563 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 4564 } 4565 4566 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 4567 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff 4568 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0 4569 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val) 4570 { 4571 return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK; 4572 } 4573 4574 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 4575 4576 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 4577 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff 4578 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0 4579 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val) 4580 { 4581 return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK; 4582 } 4583 4584 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 4585 4586 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 4587 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff 4588 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0 4589 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val) 4590 { 4591 return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK; 4592 } 4593 4594 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 4595 4596 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 4597 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 4598 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 4599 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 4600 { 4601 return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 4602 } 4603 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 4604 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 4605 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 4606 { 4607 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK; 4608 } 4609 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 4610 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 4611 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 4612 { 4613 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK; 4614 } 4615 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 4616 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 4617 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 4618 { 4619 return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 4620 } 4621 4622 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 4623 4624 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0 4625 4626 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 4627 4628 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 4629 4630 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5 4631 4632 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8 4633 4634 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9 4635 4636 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca 4637 4638 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd 4639 4640 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce 4641 4642 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf 4643 4644 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2 4645 4646 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3 4647 4648 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4 4649 4650 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 4651 4652 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 4653 4654 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9 4655 4656 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc 4657 4658 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd 4659 4660 #define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100 4661 4662 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101 4663 4664 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102 4665 4666 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103 4667 4668 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104 4669 4670 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107 4671 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 4672 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 4673 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4674 { 4675 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; 4676 } 4677 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 4678 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8 4679 static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) 4680 { 4681 return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK; 4682 } 4683 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 4684 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 4685 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4686 { 4687 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; 4688 } 4689 #define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000 4690 4691 #define REG_A5XX_RB_2D_SRC_LO 0x00002108 4692 4693 #define REG_A5XX_RB_2D_SRC_HI 0x00002109 4694 4695 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a 4696 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff 4697 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0 4698 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) 4699 { 4700 assert(!(val & 0x3f)); 4701 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; 4702 } 4703 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000 4704 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16 4705 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) 4706 { 4707 assert(!(val & 0x3f)); 4708 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; 4709 } 4710 4711 #define REG_A5XX_RB_2D_DST_INFO 0x00002110 4712 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 4713 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4714 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4715 { 4716 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 4717 } 4718 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 4719 #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 4720 static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) 4721 { 4722 return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK; 4723 } 4724 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 4725 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 4726 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4727 { 4728 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 4729 } 4730 #define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000 4731 4732 #define REG_A5XX_RB_2D_DST_LO 0x00002111 4733 4734 #define REG_A5XX_RB_2D_DST_HI 0x00002112 4735 4736 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113 4737 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff 4738 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 4739 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) 4740 { 4741 assert(!(val & 0x3f)); 4742 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; 4743 } 4744 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000 4745 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16 4746 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) 4747 { 4748 assert(!(val & 0x3f)); 4749 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; 4750 } 4751 4752 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 4753 4754 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 4755 4756 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 4757 4758 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 4759 4760 #define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180 4761 4762 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181 4763 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 4764 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 4765 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4766 { 4767 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; 4768 } 4769 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 4770 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8 4771 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) 4772 { 4773 return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK; 4774 } 4775 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 4776 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 4777 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4778 { 4779 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; 4780 } 4781 #define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000 4782 4783 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182 4784 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 4785 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4786 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4787 { 4788 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; 4789 } 4790 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300 4791 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8 4792 static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) 4793 { 4794 return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK; 4795 } 4796 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 4797 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10 4798 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4799 { 4800 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; 4801 } 4802 #define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000 4803 4804 #define REG_A5XX_UNKNOWN_2100 0x00002100 4805 4806 #define REG_A5XX_UNKNOWN_2180 0x00002180 4807 4808 #define REG_A5XX_UNKNOWN_2184 0x00002184 4809 4810 #define REG_A5XX_TEX_SAMP_0 0x00000000 4811 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 4812 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 4813 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 4814 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) 4815 { 4816 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; 4817 } 4818 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 4819 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 4820 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) 4821 { 4822 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; 4823 } 4824 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 4825 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 4826 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) 4827 { 4828 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; 4829 } 4830 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 4831 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 4832 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) 4833 { 4834 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; 4835 } 4836 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 4837 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 4838 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) 4839 { 4840 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; 4841 } 4842 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 4843 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 4844 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) 4845 { 4846 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; 4847 } 4848 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 4849 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 4850 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) 4851 { 4852 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; 4853 } 4854 4855 #define REG_A5XX_TEX_SAMP_1 0x00000001 4856 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 4857 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 4858 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 4859 { 4860 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 4861 } 4862 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 4863 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 4864 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 4865 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 4866 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 4867 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) 4868 { 4869 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; 4870 } 4871 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 4872 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 4873 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) 4874 { 4875 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; 4876 } 4877 4878 #define REG_A5XX_TEX_SAMP_2 0x00000002 4879 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0 4880 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4 4881 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 4882 { 4883 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 4884 } 4885 4886 #define REG_A5XX_TEX_SAMP_3 0x00000003 4887 4888 #define REG_A5XX_TEX_CONST_0 0x00000000 4889 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 4890 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0 4891 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) 4892 { 4893 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; 4894 } 4895 #define A5XX_TEX_CONST_0_SRGB 0x00000004 4896 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 4897 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 4898 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) 4899 { 4900 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; 4901 } 4902 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 4903 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 4904 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) 4905 { 4906 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; 4907 } 4908 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 4909 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 4910 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) 4911 { 4912 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; 4913 } 4914 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 4915 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 4916 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) 4917 { 4918 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; 4919 } 4920 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 4921 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16 4922 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) 4923 { 4924 return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK; 4925 } 4926 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 4927 #define A5XX_TEX_CONST_0_FMT__SHIFT 22 4928 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) 4929 { 4930 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; 4931 } 4932 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000 4933 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30 4934 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 4935 { 4936 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; 4937 } 4938 4939 #define REG_A5XX_TEX_CONST_1 0x00000001 4940 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 4941 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 4942 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) 4943 { 4944 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; 4945 } 4946 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 4947 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 4948 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) 4949 { 4950 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; 4951 } 4952 4953 #define REG_A5XX_TEX_CONST_2 0x00000002 4954 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 4955 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 4956 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) 4957 { 4958 return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; 4959 } 4960 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 4961 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7 4962 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) 4963 { 4964 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; 4965 } 4966 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 4967 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29 4968 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) 4969 { 4970 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; 4971 } 4972 4973 #define REG_A5XX_TEX_CONST_3 0x00000003 4974 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 4975 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 4976 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 4977 { 4978 assert(!(val & 0xfff)); 4979 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; 4980 } 4981 #define A5XX_TEX_CONST_3_FLAG 0x10000000 4982 4983 #define REG_A5XX_TEX_CONST_4 0x00000004 4984 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 4985 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 4986 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) 4987 { 4988 assert(!(val & 0x1f)); 4989 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; 4990 } 4991 4992 #define REG_A5XX_TEX_CONST_5 0x00000005 4993 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 4994 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0 4995 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) 4996 { 4997 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; 4998 } 4999 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 5000 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 5001 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) 5002 { 5003 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; 5004 } 5005 5006 #define REG_A5XX_TEX_CONST_6 0x00000006 5007 5008 #define REG_A5XX_TEX_CONST_7 0x00000007 5009 5010 #define REG_A5XX_TEX_CONST_8 0x00000008 5011 5012 #define REG_A5XX_TEX_CONST_9 0x00000009 5013 5014 #define REG_A5XX_TEX_CONST_10 0x0000000a 5015 5016 #define REG_A5XX_TEX_CONST_11 0x0000000b 5017 5018 #define REG_A5XX_SSBO_0_0 0x00000000 5019 #define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0 5020 #define A5XX_SSBO_0_0_BASE_LO__SHIFT 5 5021 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) 5022 { 5023 assert(!(val & 0x1f)); 5024 return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK; 5025 } 5026 5027 #define REG_A5XX_SSBO_0_1 0x00000001 5028 #define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff 5029 #define A5XX_SSBO_0_1_PITCH__SHIFT 0 5030 static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) 5031 { 5032 return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK; 5033 } 5034 5035 #define REG_A5XX_SSBO_0_2 0x00000002 5036 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 5037 #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 5038 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) 5039 { 5040 assert(!(val & 0xfff)); 5041 return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK; 5042 } 5043 5044 #define REG_A5XX_SSBO_0_3 0x00000003 5045 #define A5XX_SSBO_0_3_CPP__MASK 0x0000003f 5046 #define A5XX_SSBO_0_3_CPP__SHIFT 0 5047 static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val) 5048 { 5049 return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK; 5050 } 5051 5052 #define REG_A5XX_SSBO_1_0 0x00000000 5053 #define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00 5054 #define A5XX_SSBO_1_0_FMT__SHIFT 8 5055 static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) 5056 { 5057 return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK; 5058 } 5059 #define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000 5060 #define A5XX_SSBO_1_0_WIDTH__SHIFT 16 5061 static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val) 5062 { 5063 return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK; 5064 } 5065 5066 #define REG_A5XX_SSBO_1_1 0x00000001 5067 #define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff 5068 #define A5XX_SSBO_1_1_HEIGHT__SHIFT 0 5069 static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val) 5070 { 5071 return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK; 5072 } 5073 #define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000 5074 #define A5XX_SSBO_1_1_DEPTH__SHIFT 16 5075 static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val) 5076 { 5077 return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK; 5078 } 5079 5080 #define REG_A5XX_SSBO_2_0 0x00000000 5081 #define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff 5082 #define A5XX_SSBO_2_0_BASE_LO__SHIFT 0 5083 static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val) 5084 { 5085 return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK; 5086 } 5087 5088 #define REG_A5XX_SSBO_2_1 0x00000001 5089 #define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff 5090 #define A5XX_SSBO_2_1_BASE_HI__SHIFT 0 5091 static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val) 5092 { 5093 return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK; 5094 } 5095 5096 5097 #endif /* A5XX_XML */ 5098
