1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the pass that finds instructions that can be 11 // re-written as LEA instructions in order to reduce pipeline delays. 12 // When optimizing for size it replaces suitable LEAs with INC or DEC. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86.h" 17 #include "X86InstrInfo.h" 18 #include "X86Subtarget.h" 19 #include "llvm/ADT/Statistic.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/Passes.h" 23 #include "llvm/CodeGen/TargetSchedule.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/raw_ostream.h" 26 using namespace llvm; 27 28 namespace llvm { 29 void initializeFixupLEAPassPass(PassRegistry &); 30 } 31 32 #define FIXUPLEA_DESC "X86 LEA Fixup" 33 #define FIXUPLEA_NAME "x86-fixup-LEAs" 34 35 #define DEBUG_TYPE FIXUPLEA_NAME 36 37 STATISTIC(NumLEAs, "Number of LEA instructions created"); 38 39 namespace { 40 class FixupLEAPass : public MachineFunctionPass { 41 enum RegUsageState { RU_NotUsed, RU_Write, RU_Read }; 42 43 /// Loop over all of the instructions in the basic block 44 /// replacing applicable instructions with LEA instructions, 45 /// where appropriate. 46 bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI); 47 48 49 /// Given a machine register, look for the instruction 50 /// which writes it in the current basic block. If found, 51 /// try to replace it with an equivalent LEA instruction. 52 /// If replacement succeeds, then also process the newly created 53 /// instruction. 54 void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I, 55 MachineFunction::iterator MFI); 56 57 /// Given a memory access or LEA instruction 58 /// whose address mode uses a base and/or index register, look for 59 /// an opportunity to replace the instruction which sets the base or index 60 /// register with an equivalent LEA instruction. 61 void processInstruction(MachineBasicBlock::iterator &I, 62 MachineFunction::iterator MFI); 63 64 /// Given a LEA instruction which is unprofitable 65 /// on Silvermont try to replace it with an equivalent ADD instruction 66 void processInstructionForSLM(MachineBasicBlock::iterator &I, 67 MachineFunction::iterator MFI); 68 69 70 /// Given a LEA instruction which is unprofitable 71 /// on SNB+ try to replace it with other instructions. 72 /// According to Intel's Optimization Reference Manual: 73 /// " For LEA instructions with three source operands and some specific 74 /// situations, instruction latency has increased to 3 cycles, and must 75 /// dispatch via port 1: 76 /// - LEA that has all three source operands: base, index, and offset 77 /// - LEA that uses base and index registers where the base is EBP, RBP, 78 /// or R13 79 /// - LEA that uses RIP relative addressing mode 80 /// - LEA that uses 16-bit addressing mode " 81 /// This function currently handles the first 2 cases only. 82 MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI, 83 MachineFunction::iterator MFI); 84 85 /// Look for LEAs that add 1 to reg or subtract 1 from reg 86 /// and convert them to INC or DEC respectively. 87 bool fixupIncDec(MachineBasicBlock::iterator &I, 88 MachineFunction::iterator MFI) const; 89 90 /// Determine if an instruction references a machine register 91 /// and, if so, whether it reads or writes the register. 92 RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I); 93 94 /// Step backwards through a basic block, looking 95 /// for an instruction which writes a register within 96 /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles. 97 MachineBasicBlock::iterator searchBackwards(MachineOperand &p, 98 MachineBasicBlock::iterator &I, 99 MachineFunction::iterator MFI); 100 101 /// if an instruction can be converted to an 102 /// equivalent LEA, insert the new instruction into the basic block 103 /// and return a pointer to it. Otherwise, return zero. 104 MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI, 105 MachineBasicBlock::iterator &MBBI) const; 106 107 public: 108 static char ID; 109 110 StringRef getPassName() const override { return FIXUPLEA_DESC; } 111 112 FixupLEAPass() : MachineFunctionPass(ID) { 113 initializeFixupLEAPassPass(*PassRegistry::getPassRegistry()); 114 } 115 116 /// Loop over all of the basic blocks, 117 /// replacing instructions by equivalent LEA instructions 118 /// if needed and when possible. 119 bool runOnMachineFunction(MachineFunction &MF) override; 120 121 // This pass runs after regalloc and doesn't support VReg operands. 122 MachineFunctionProperties getRequiredProperties() const override { 123 return MachineFunctionProperties().set( 124 MachineFunctionProperties::Property::NoVRegs); 125 } 126 127 private: 128 TargetSchedModel TSM; 129 MachineFunction *MF; 130 const X86InstrInfo *TII; // Machine instruction info. 131 bool OptIncDec; 132 bool OptLEA; 133 }; 134 } 135 136 char FixupLEAPass::ID = 0; 137 138 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false) 139 140 MachineInstr * 141 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI, 142 MachineBasicBlock::iterator &MBBI) const { 143 MachineInstr &MI = *MBBI; 144 switch (MI.getOpcode()) { 145 case X86::MOV32rr: 146 case X86::MOV64rr: { 147 const MachineOperand &Src = MI.getOperand(1); 148 const MachineOperand &Dest = MI.getOperand(0); 149 MachineInstr *NewMI = 150 BuildMI(*MF, MI.getDebugLoc(), 151 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r 152 : X86::LEA64r)) 153 .add(Dest) 154 .add(Src) 155 .addImm(1) 156 .addReg(0) 157 .addImm(0) 158 .addReg(0); 159 MFI->insert(MBBI, NewMI); // Insert the new inst 160 return NewMI; 161 } 162 case X86::ADD64ri32: 163 case X86::ADD64ri8: 164 case X86::ADD64ri32_DB: 165 case X86::ADD64ri8_DB: 166 case X86::ADD32ri: 167 case X86::ADD32ri8: 168 case X86::ADD32ri_DB: 169 case X86::ADD32ri8_DB: 170 case X86::ADD16ri: 171 case X86::ADD16ri8: 172 case X86::ADD16ri_DB: 173 case X86::ADD16ri8_DB: 174 if (!MI.getOperand(2).isImm()) { 175 // convertToThreeAddress will call getImm() 176 // which requires isImm() to be true 177 return nullptr; 178 } 179 break; 180 case X86::ADD16rr: 181 case X86::ADD16rr_DB: 182 if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) { 183 // if src1 != src2, then convertToThreeAddress will 184 // need to create a Virtual register, which we cannot do 185 // after register allocation. 186 return nullptr; 187 } 188 } 189 return TII->convertToThreeAddress(MFI, MI, nullptr); 190 } 191 192 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); } 193 194 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) { 195 if (skipFunction(Func.getFunction())) 196 return false; 197 198 MF = &Func; 199 const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>(); 200 OptIncDec = !ST.slowIncDec() || Func.getFunction().optForMinSize(); 201 OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA(); 202 203 if (!OptLEA && !OptIncDec) 204 return false; 205 206 TSM.init(&Func.getSubtarget()); 207 TII = ST.getInstrInfo(); 208 209 LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";); 210 // Process all basic blocks. 211 for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I) 212 processBasicBlock(Func, I); 213 LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";); 214 215 return true; 216 } 217 218 FixupLEAPass::RegUsageState 219 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) { 220 RegUsageState RegUsage = RU_NotUsed; 221 MachineInstr &MI = *I; 222 223 for (unsigned int i = 0; i < MI.getNumOperands(); ++i) { 224 MachineOperand &opnd = MI.getOperand(i); 225 if (opnd.isReg() && opnd.getReg() == p.getReg()) { 226 if (opnd.isDef()) 227 return RU_Write; 228 RegUsage = RU_Read; 229 } 230 } 231 return RegUsage; 232 } 233 234 /// getPreviousInstr - Given a reference to an instruction in a basic 235 /// block, return a reference to the previous instruction in the block, 236 /// wrapping around to the last instruction of the block if the block 237 /// branches to itself. 238 static inline bool getPreviousInstr(MachineBasicBlock::iterator &I, 239 MachineFunction::iterator MFI) { 240 if (I == MFI->begin()) { 241 if (MFI->isPredecessor(&*MFI)) { 242 I = --MFI->end(); 243 return true; 244 } else 245 return false; 246 } 247 --I; 248 return true; 249 } 250 251 MachineBasicBlock::iterator 252 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I, 253 MachineFunction::iterator MFI) { 254 int InstrDistance = 1; 255 MachineBasicBlock::iterator CurInst; 256 static const int INSTR_DISTANCE_THRESHOLD = 5; 257 258 CurInst = I; 259 bool Found; 260 Found = getPreviousInstr(CurInst, MFI); 261 while (Found && I != CurInst) { 262 if (CurInst->isCall() || CurInst->isInlineAsm()) 263 break; 264 if (InstrDistance > INSTR_DISTANCE_THRESHOLD) 265 break; // too far back to make a difference 266 if (usesRegister(p, CurInst) == RU_Write) { 267 return CurInst; 268 } 269 InstrDistance += TSM.computeInstrLatency(&*CurInst); 270 Found = getPreviousInstr(CurInst, MFI); 271 } 272 return MachineBasicBlock::iterator(); 273 } 274 275 static inline bool isLEA(const int Opcode) { 276 return Opcode == X86::LEA16r || Opcode == X86::LEA32r || 277 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r; 278 } 279 280 static inline bool isInefficientLEAReg(unsigned int Reg) { 281 return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13; 282 } 283 284 static inline bool isRegOperand(const MachineOperand &Op) { 285 return Op.isReg() && Op.getReg() != X86::NoRegister; 286 } 287 /// hasIneffecientLEARegs - LEA that uses base and index registers 288 /// where the base is EBP, RBP, or R13 289 // TODO: use a variant scheduling class to model the latency profile 290 // of LEA instructions, and implement this logic as a scheduling predicate. 291 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base, 292 const MachineOperand &Index) { 293 return Base.isReg() && isInefficientLEAReg(Base.getReg()) && 294 isRegOperand(Index); 295 } 296 297 static inline bool hasLEAOffset(const MachineOperand &Offset) { 298 return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal(); 299 } 300 301 static inline int getADDrrFromLEA(int LEAOpcode) { 302 switch (LEAOpcode) { 303 default: 304 llvm_unreachable("Unexpected LEA instruction"); 305 case X86::LEA16r: 306 return X86::ADD16rr; 307 case X86::LEA32r: 308 return X86::ADD32rr; 309 case X86::LEA64_32r: 310 case X86::LEA64r: 311 return X86::ADD64rr; 312 } 313 } 314 315 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) { 316 bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm()); 317 switch (LEAOpcode) { 318 default: 319 llvm_unreachable("Unexpected LEA instruction"); 320 case X86::LEA16r: 321 return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri; 322 case X86::LEA32r: 323 case X86::LEA64_32r: 324 return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri; 325 case X86::LEA64r: 326 return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32; 327 } 328 } 329 330 /// isLEASimpleIncOrDec - Does this LEA have one these forms: 331 /// lea %reg, 1(%reg) 332 /// lea %reg, -1(%reg) 333 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) { 334 unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg(); 335 unsigned DstReg = LEA.getOperand(0).getReg(); 336 unsigned AddrDispOp = 1 + X86::AddrDisp; 337 return SrcReg == DstReg && 338 LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && 339 LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && 340 LEA.getOperand(AddrDispOp).isImm() && 341 (LEA.getOperand(AddrDispOp).getImm() == 1 || 342 LEA.getOperand(AddrDispOp).getImm() == -1); 343 } 344 345 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I, 346 MachineFunction::iterator MFI) const { 347 MachineInstr &MI = *I; 348 int Opcode = MI.getOpcode(); 349 if (!isLEA(Opcode)) 350 return false; 351 352 if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) { 353 int NewOpcode; 354 bool isINC = MI.getOperand(4).getImm() == 1; 355 switch (Opcode) { 356 case X86::LEA16r: 357 NewOpcode = isINC ? X86::INC16r : X86::DEC16r; 358 break; 359 case X86::LEA32r: 360 case X86::LEA64_32r: 361 NewOpcode = isINC ? X86::INC32r : X86::DEC32r; 362 break; 363 case X86::LEA64r: 364 NewOpcode = isINC ? X86::INC64r : X86::DEC64r; 365 break; 366 } 367 368 MachineInstr *NewMI = 369 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode)) 370 .add(MI.getOperand(0)) 371 .add(MI.getOperand(1)); 372 MFI->erase(I); 373 I = static_cast<MachineBasicBlock::iterator>(NewMI); 374 return true; 375 } 376 return false; 377 } 378 379 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I, 380 MachineFunction::iterator MFI) { 381 // Process a load, store, or LEA instruction. 382 MachineInstr &MI = *I; 383 const MCInstrDesc &Desc = MI.getDesc(); 384 int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags); 385 if (AddrOffset >= 0) { 386 AddrOffset += X86II::getOperandBias(Desc); 387 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); 388 if (p.isReg() && p.getReg() != X86::ESP) { 389 seekLEAFixup(p, I, MFI); 390 } 391 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); 392 if (q.isReg() && q.getReg() != X86::ESP) { 393 seekLEAFixup(q, I, MFI); 394 } 395 } 396 } 397 398 void FixupLEAPass::seekLEAFixup(MachineOperand &p, 399 MachineBasicBlock::iterator &I, 400 MachineFunction::iterator MFI) { 401 MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI); 402 if (MBI != MachineBasicBlock::iterator()) { 403 MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI); 404 if (NewMI) { 405 ++NumLEAs; 406 LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump();); 407 // now to replace with an equivalent LEA... 408 LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump();); 409 MFI->erase(MBI); 410 MachineBasicBlock::iterator J = 411 static_cast<MachineBasicBlock::iterator>(NewMI); 412 processInstruction(J, MFI); 413 } 414 } 415 } 416 417 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I, 418 MachineFunction::iterator MFI) { 419 MachineInstr &MI = *I; 420 const int Opcode = MI.getOpcode(); 421 if (!isLEA(Opcode)) 422 return; 423 if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() || 424 !TII->isSafeToClobberEFLAGS(*MFI, I)) 425 return; 426 const unsigned DstR = MI.getOperand(0).getReg(); 427 const unsigned SrcR1 = MI.getOperand(1).getReg(); 428 const unsigned SrcR2 = MI.getOperand(3).getReg(); 429 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) 430 return; 431 if (MI.getOperand(2).getImm() > 1) 432 return; 433 LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump();); 434 LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";); 435 MachineInstr *NewMI = nullptr; 436 // Make ADD instruction for two registers writing to LEA's destination 437 if (SrcR1 != 0 && SrcR2 != 0) { 438 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode)); 439 const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1); 440 NewMI = 441 BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src); 442 LLVM_DEBUG(NewMI->dump();); 443 } 444 // Make ADD instruction for immediate 445 if (MI.getOperand(4).getImm() != 0) { 446 const MCInstrDesc &ADDri = 447 TII->get(getADDriFromLEA(Opcode, MI.getOperand(4))); 448 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); 449 NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR) 450 .add(SrcR) 451 .addImm(MI.getOperand(4).getImm()); 452 LLVM_DEBUG(NewMI->dump();); 453 } 454 if (NewMI) { 455 MFI->erase(I); 456 I = NewMI; 457 } 458 } 459 460 MachineInstr * 461 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, 462 MachineFunction::iterator MFI) { 463 464 const int LEAOpcode = MI.getOpcode(); 465 if (!isLEA(LEAOpcode)) 466 return nullptr; 467 468 const MachineOperand &Dst = MI.getOperand(0); 469 const MachineOperand &Base = MI.getOperand(1); 470 const MachineOperand &Scale = MI.getOperand(2); 471 const MachineOperand &Index = MI.getOperand(3); 472 const MachineOperand &Offset = MI.getOperand(4); 473 const MachineOperand &Segment = MI.getOperand(5); 474 475 if (!(TII->isThreeOperandsLEA(MI) || 476 hasInefficientLEABaseReg(Base, Index)) || 477 !TII->isSafeToClobberEFLAGS(*MFI, MI) || 478 Segment.getReg() != X86::NoRegister) 479 return nullptr; 480 481 unsigned int DstR = Dst.getReg(); 482 unsigned int BaseR = Base.getReg(); 483 unsigned int IndexR = Index.getReg(); 484 unsigned SSDstR = 485 (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR; 486 bool IsScale1 = Scale.getImm() == 1; 487 bool IsInefficientBase = isInefficientLEAReg(BaseR); 488 bool IsInefficientIndex = isInefficientLEAReg(IndexR); 489 490 // Skip these cases since it takes more than 2 instructions 491 // to replace the LEA instruction. 492 if (IsInefficientBase && SSDstR == BaseR && !IsScale1) 493 return nullptr; 494 if (LEAOpcode == X86::LEA64_32r && IsInefficientBase && 495 (IsInefficientIndex || !IsScale1)) 496 return nullptr; 497 498 const DebugLoc DL = MI.getDebugLoc(); 499 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode)); 500 const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset)); 501 502 LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump();); 503 LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";); 504 505 // First try to replace LEA with one or two (for the 3-op LEA case) 506 // add instructions: 507 // 1.lea (%base,%index,1), %base => add %index,%base 508 // 2.lea (%base,%index,1), %index => add %base,%index 509 if (IsScale1 && (DstR == BaseR || DstR == IndexR)) { 510 const MachineOperand &Src = DstR == BaseR ? Index : Base; 511 MachineInstr *NewMI = 512 BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src); 513 LLVM_DEBUG(NewMI->dump();); 514 // Create ADD instruction for the Offset in case of 3-Ops LEA. 515 if (hasLEAOffset(Offset)) { 516 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); 517 LLVM_DEBUG(NewMI->dump();); 518 } 519 return NewMI; 520 } 521 // If the base is inefficient try switching the index and base operands, 522 // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction: 523 // lea offset(%base,%index,scale),%dst => 524 // lea (%base,%index,scale); add offset,%dst 525 if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) { 526 MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode)) 527 .add(Dst) 528 .add(IsInefficientBase ? Index : Base) 529 .add(Scale) 530 .add(IsInefficientBase ? Base : Index) 531 .addImm(0) 532 .add(Segment); 533 LLVM_DEBUG(NewMI->dump();); 534 // Create ADD instruction for the Offset in case of 3-Ops LEA. 535 if (hasLEAOffset(Offset)) { 536 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); 537 LLVM_DEBUG(NewMI->dump();); 538 } 539 return NewMI; 540 } 541 // Handle the rest of the cases with inefficient base register: 542 assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!"); 543 assert(IsInefficientBase && "efficient base should be handled already!"); 544 545 // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst 546 if (IsScale1 && !hasLEAOffset(Offset)) { 547 bool BIK = Base.isKill() && BaseR != IndexR; 548 TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK); 549 LLVM_DEBUG(MI.getPrevNode()->dump();); 550 551 MachineInstr *NewMI = 552 BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index); 553 LLVM_DEBUG(NewMI->dump();); 554 return NewMI; 555 } 556 // lea offset(%base,%index,scale), %dst => 557 // lea offset( ,%index,scale), %dst; add %base,%dst 558 MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode)) 559 .add(Dst) 560 .addReg(0) 561 .add(Scale) 562 .add(Index) 563 .add(Offset) 564 .add(Segment); 565 LLVM_DEBUG(NewMI->dump();); 566 567 NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base); 568 LLVM_DEBUG(NewMI->dump();); 569 return NewMI; 570 } 571 572 bool FixupLEAPass::processBasicBlock(MachineFunction &MF, 573 MachineFunction::iterator MFI) { 574 575 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) { 576 if (OptIncDec) 577 if (fixupIncDec(I, MFI)) 578 continue; 579 580 if (OptLEA) { 581 if (MF.getSubtarget<X86Subtarget>().slowLEA()) 582 processInstructionForSLM(I, MFI); 583 584 else { 585 if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) { 586 if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) { 587 MFI->erase(I); 588 I = NewMI; 589 } 590 } else 591 processInstruction(I, MFI); 592 } 593 } 594 } 595 return false; 596 } 597
