1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Andes Technology Corporation 4 * Shawn Lin, Andes Technology Corporation <nobuhiro (at) andestech.com> 5 * Macpaul Lin, Andes Technology Corporation <macpaul (at) andestech.com> 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <asm/arch-ag101/ag101.h> 12 13 /* 14 * CPU and Board Configuration Options 15 */ 16 #define CONFIG_USE_INTERRUPT 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 #define CONFIG_ARCH_MAP_SYSMEM 21 22 #define CONFIG_BOOTP_SEND_HOSTNAME 23 #define CONFIG_BOOTP_SERVERIP 24 25 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 26 #define CONFIG_MEM_REMAP 27 #endif 28 29 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 30 #ifdef CONFIG_OF_CONTROL 31 #undef CONFIG_OF_SEPARATE 32 #define CONFIG_OF_EMBED 33 #endif 34 #endif 35 36 /* 37 * Timer 38 */ 39 #define CONFIG_SYS_CLK_FREQ 39062500 40 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 41 42 /* 43 * Use Externel CLOCK or PCLK 44 */ 45 #undef CONFIG_FTRTC010_EXTCLK 46 47 #ifndef CONFIG_FTRTC010_EXTCLK 48 #define CONFIG_FTRTC010_PCLK 49 #endif 50 51 #ifdef CONFIG_FTRTC010_EXTCLK 52 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 53 #else 54 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 55 #endif 56 57 #define TIMER_LOAD_VAL 0xffffffff 58 59 /* 60 * Real Time Clock 61 */ 62 #define CONFIG_RTC_FTRTC010 63 64 /* 65 * Real Time Clock Divider 66 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 67 */ 68 #define OSC_5MHZ (5*1000000) 69 #define OSC_CLK (4*OSC_5MHZ) 70 #define RTC_DIV_COUNT (0.5) /* Why?? */ 71 72 /* 73 * Serial console configuration 74 */ 75 76 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 77 #define CONFIG_SYS_NS16550_SERIAL 78 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 79 #ifndef CONFIG_DM_SERIAL 80 #define CONFIG_SYS_NS16550_REG_SIZE -4 81 #endif 82 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 83 84 /* 85 * Miscellaneous configurable options 86 */ 87 88 /* 89 * Size of malloc() pool 90 */ 91 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 92 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 93 94 /* 95 * AHB Controller configuration 96 */ 97 #define CONFIG_FTAHBC020S 98 99 #ifdef CONFIG_FTAHBC020S 100 #include <faraday/ftahbc020s.h> 101 102 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 103 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 104 105 /* 106 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 107 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 108 * in C language. 109 */ 110 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 111 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 112 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 113 #endif 114 115 /* 116 * Watchdog 117 */ 118 #define CONFIG_FTWDT010_WATCHDOG 119 120 /* 121 * PMU Power controller configuration 122 */ 123 #define CONFIG_PMU 124 #define CONFIG_FTPMU010_POWER 125 126 #ifdef CONFIG_FTPMU010_POWER 127 #include <faraday/ftpmu010.h> 128 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 129 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 130 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 131 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 132 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 133 FTPMU010_SDRAMHTC_CKE_DCSR | \ 134 FTPMU010_SDRAMHTC_DQM_DCSR | \ 135 FTPMU010_SDRAMHTC_SDCLK_DCSR) 136 #endif 137 138 /* 139 * SDRAM controller configuration 140 */ 141 #define CONFIG_FTSDMC021 142 143 #ifdef CONFIG_FTSDMC021 144 #include <faraday/ftsdmc021.h> 145 146 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 147 FTSDMC021_TP1_TRP(1) | \ 148 FTSDMC021_TP1_TRCD(1) | \ 149 FTSDMC021_TP1_TRF(3) | \ 150 FTSDMC021_TP1_TWR(1) | \ 151 FTSDMC021_TP1_TCL(2)) 152 153 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 154 FTSDMC021_TP2_INI_REFT(8) | \ 155 FTSDMC021_TP2_REF_INTV(0x180)) 156 157 /* 158 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 159 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 160 * C language. 161 */ 162 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 163 FTSDMC021_CR1_DSZ(3) | \ 164 FTSDMC021_CR1_MBW(2) | \ 165 FTSDMC021_CR1_BNKSIZE(6)) 166 167 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 168 FTSDMC021_CR2_IREF | \ 169 FTSDMC021_CR2_ISMR) 170 171 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 172 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 173 CONFIG_SYS_FTSDMC021_BANK0_BASE) 174 175 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 176 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 177 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 178 CONFIG_SYS_FTSDMC021_BANK1_BASE) 179 #endif 180 181 /* 182 * Physical Memory Map 183 */ 184 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 185 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 186 #else 187 #ifdef CONFIG_MEM_REMAP 188 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 189 #else 190 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 191 #endif 192 #endif 193 194 #define PHYS_SDRAM_1 \ 195 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 196 197 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 198 199 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 200 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 201 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 202 #else 203 #ifdef CONFIG_MEM_REMAP 204 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 205 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 206 #else 207 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 208 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 209 #endif 210 #endif 211 212 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 213 214 #ifdef CONFIG_MEM_REMAP 215 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 216 GENERATED_GBL_DATA_SIZE) 217 #else 218 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 219 GENERATED_GBL_DATA_SIZE) 220 #endif /* CONFIG_MEM_REMAP */ 221 222 /* 223 * Load address and memory test area should agree with 224 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 225 */ 226 #define CONFIG_SYS_LOAD_ADDR 0x300000 227 228 /* memtest works on 63 MB in DRAM */ 229 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 230 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 231 232 /* 233 * Static memory controller configuration 234 */ 235 #define CONFIG_FTSMC020 236 237 #ifdef CONFIG_FTSMC020 238 #include <faraday/ftsmc020.h> 239 240 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 241 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 242 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 243 } 244 245 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 246 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 247 FTSMC020_BANK_SIZE_32M | \ 248 FTSMC020_BANK_MBW_32) 249 250 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 251 FTSMC020_TPR_AST(1) | \ 252 FTSMC020_TPR_CTW(1) | \ 253 FTSMC020_TPR_ATI(1) | \ 254 FTSMC020_TPR_AT2(1) | \ 255 FTSMC020_TPR_WTC(1) | \ 256 FTSMC020_TPR_AHT(1) | \ 257 FTSMC020_TPR_TRNA(1)) 258 #endif 259 260 /* 261 * FLASH on ADP_AG101P is connected to BANK0 262 * Just disalbe the other BANK to avoid detection error. 263 */ 264 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 265 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 266 FTSMC020_BANK_SIZE_32M | \ 267 FTSMC020_BANK_MBW_32) 268 269 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 270 FTSMC020_TPR_CTW(3) | \ 271 FTSMC020_TPR_ATI(0xf) | \ 272 FTSMC020_TPR_AT2(3) | \ 273 FTSMC020_TPR_WTC(3) | \ 274 FTSMC020_TPR_AHT(3) | \ 275 FTSMC020_TPR_TRNA(0xf)) 276 277 #define FTSMC020_BANK1_CONFIG (0x00) 278 #define FTSMC020_BANK1_TIMING (0x00) 279 #endif /* CONFIG_FTSMC020 */ 280 281 /* 282 * FLASH and environment organization 283 */ 284 /* use CFI framework */ 285 #define CONFIG_SYS_FLASH_CFI 286 #define CONFIG_FLASH_CFI_DRIVER 287 288 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 289 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 290 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 291 292 /* support JEDEC */ 293 294 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 295 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 296 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 297 #else 298 #ifdef CONFIG_MEM_REMAP 299 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 300 #else 301 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 302 #endif 303 #endif /* CONFIG_MEM_REMAP */ 304 305 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 306 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 307 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 308 309 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 310 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 311 312 /* max number of memory banks */ 313 /* 314 * There are 4 banks supported for this Controller, 315 * but we have only 1 bank connected to flash on board 316 */ 317 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 318 #define CONFIG_SYS_MAX_FLASH_BANKS 1 319 #endif 320 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 321 322 /* max number of sectors on one chip */ 323 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 324 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 325 #define CONFIG_SYS_MAX_FLASH_SECT 512 326 327 /* environments */ 328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 329 #define CONFIG_ENV_SIZE 8192 330 #define CONFIG_ENV_OVERWRITE 331 332 /* 333 * For booting Linux, the board info and command line data 334 * have to be in the first 16 MB of memory, since this is 335 * the maximum mapped by the Linux kernel during initialization. 336 */ 337 338 /* Initial Memory map for Linux*/ 339 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 340 /* Increase max gunzip size */ 341 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 342 343 #endif /* __CONFIG_H */ 344
