1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2015 Arcturus Networks, Inc. 4 * http://www.arcturusnetworks.com/products/ucp1020/ 5 * based on include/configs/p1_p2_rdb_pc.h 6 * original copyright follows: 7 * Copyright 2009-2011 Freescale Semiconductor, Inc. 8 */ 9 10 /* 11 * QorIQ uCP1020-xx boards configuration file 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 17 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 18 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 19 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 20 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 21 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 22 23 #if defined(CONFIG_TARTGET_UCP1020T1) 24 25 #define CONFIG_UCP1020_REV_1_3 26 27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 28 29 #define CONFIG_TSEC1 30 #define CONFIG_TSEC3 31 #define CONFIG_HAS_ETH0 32 #define CONFIG_HAS_ETH1 33 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 34 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 35 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 36 #define CONFIG_IPADDR 10.80.41.229 37 #define CONFIG_SERVERIP 10.80.41.227 38 #define CONFIG_NETMASK 255.255.252.0 39 #define CONFIG_ETHPRIME "eTSEC3" 40 41 #ifndef CONFIG_SPI_FLASH 42 #endif 43 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 44 45 #define CONFIG_SYS_L2_SIZE (256 << 10) 46 47 #endif 48 49 #if defined(CONFIG_TARGET_UCP1020) 50 51 #define CONFIG_UCP1020 52 #define CONFIG_UCP1020_REV_1_3 53 54 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 55 56 #define CONFIG_TSEC1 57 #define CONFIG_TSEC2 58 #define CONFIG_TSEC3 59 #define CONFIG_HAS_ETH0 60 #define CONFIG_HAS_ETH1 61 #define CONFIG_HAS_ETH2 62 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 63 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 64 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 65 #define CONFIG_IPADDR 192.168.1.81 66 #define CONFIG_IPADDR1 192.168.1.82 67 #define CONFIG_IPADDR2 192.168.1.83 68 #define CONFIG_SERVERIP 192.168.1.80 69 #define CONFIG_GATEWAYIP 102.168.1.1 70 #define CONFIG_NETMASK 255.255.255.0 71 #define CONFIG_ETHPRIME "eTSEC1" 72 73 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 77 #endif 78 79 #ifdef CONFIG_SDCARD 80 #define CONFIG_RAMBOOT_SDCARD 81 #define CONFIG_SYS_RAMBOOT 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 84 #endif 85 86 #ifdef CONFIG_SPIFLASH 87 #define CONFIG_RAMBOOT_SPIFLASH 88 #define CONFIG_SYS_RAMBOOT 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 91 #endif 92 93 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 94 95 #ifndef CONFIG_RESET_VECTOR_ADDRESS 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 97 #endif 98 99 #ifndef CONFIG_SYS_MONITOR_BASE 100 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 101 #endif 102 103 #define CONFIG_MP 104 105 #define CONFIG_ENV_OVERWRITE 106 107 #define CONFIG_SYS_SATA_MAX_DEVICE 2 108 #define CONFIG_LBA48 109 110 #define CONFIG_SYS_CLK_FREQ 66666666 111 #define CONFIG_DDR_CLK_FREQ 66666666 112 113 #define CONFIG_HWCONFIG 114 115 /* 116 * These can be toggled for performance analysis, otherwise use default. 117 */ 118 #define CONFIG_L2_CACHE 119 #define CONFIG_BTB 120 121 #define CONFIG_ENABLE_36BIT_PHYS 122 123 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 124 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 125 126 #define CONFIG_SYS_CCSRBAR 0xffe00000 127 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 128 129 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 130 SPL code*/ 131 #ifdef CONFIG_SPL_BUILD 132 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 133 #endif 134 135 /* DDR Setup */ 136 #define CONFIG_DDR_ECC_ENABLE 137 #ifndef CONFIG_DDR_ECC_ENABLE 138 #define CONFIG_SYS_DDR_RAW_TIMING 139 #define CONFIG_DDR_SPD 140 #endif 141 #define CONFIG_SYS_SPD_BUS_NUM 1 142 #undef CONFIG_FSL_DDR_INTERACTIVE 143 144 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 145 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 146 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 149 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 152 /* Default settings for DDR3 */ 153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 154 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 155 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 156 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 157 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 158 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 159 160 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 161 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 162 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 163 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 164 165 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 166 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 167 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 168 #define CONFIG_SYS_DDR_RCW_1 0x00000000 169 #define CONFIG_SYS_DDR_RCW_2 0x00000000 170 #ifdef CONFIG_DDR_ECC_ENABLE 171 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 172 #else 173 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 174 #endif 175 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 176 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 177 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 178 179 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 180 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 181 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 182 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 183 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 184 #define CONFIG_SYS_DDR_MODE_1 0x40461520 185 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 186 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 187 188 #undef CONFIG_CLOCKS_IN_MHZ 189 190 /* 191 * Memory map 192 * 193 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 194 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 195 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 196 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 197 * (early boot only) 198 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 199 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 200 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 201 */ 202 203 /* 204 * Local Bus Definitions 205 */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 207 #define CONFIG_SYS_FLASH_BASE 0xec000000 208 209 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 210 211 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 212 | BR_PS_16 | BR_V) 213 214 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 215 216 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 217 #define CONFIG_SYS_FLASH_QUIET_TEST 218 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 219 220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 221 222 #undef CONFIG_SYS_FLASH_CHECKSUM 223 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 225 226 #define CONFIG_FLASH_CFI_DRIVER 227 #define CONFIG_SYS_FLASH_CFI 228 #define CONFIG_SYS_FLASH_EMPTY_INFO 229 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 230 231 #define CONFIG_SYS_INIT_RAM_LOCK 232 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 233 /* Initial L1 address */ 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 237 /* Size of used area in RAM */ 238 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 239 240 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 241 GENERATED_GBL_DATA_SIZE) 242 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 243 244 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 245 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 246 247 #define CONFIG_SYS_PMC_BASE 0xff980000 248 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 249 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 250 BR_PS_8 | BR_V) 251 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 252 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 253 OR_GPCM_EAD) 254 255 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 256 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 257 #ifdef CONFIG_NAND_FSL_ELBC 258 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 259 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 260 #endif 261 262 /* Serial Port - controlled on board with jumper J8 263 * open - index 2 264 * shorted - index 1 265 */ 266 #undef CONFIG_SERIAL_SOFTWARE_FIFO 267 #define CONFIG_SYS_NS16550_SERIAL 268 #define CONFIG_SYS_NS16550_REG_SIZE 1 269 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 270 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 271 #define CONFIG_NS16550_MIN_FUNCTIONS 272 #endif 273 274 #define CONFIG_SYS_BAUDRATE_TABLE \ 275 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 276 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 279 280 /* I2C */ 281 #define CONFIG_SYS_I2C 282 #define CONFIG_SYS_I2C_FSL 283 #define CONFIG_SYS_FSL_I2C_SPEED 400000 284 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 285 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 286 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 287 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 288 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 289 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 290 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 291 292 #define CONFIG_RTC_DS1337 293 #define CONFIG_RTC_DS1337_NOOSC 294 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 295 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 296 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 297 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 298 299 /* 300 * eSPI - Enhanced SPI 301 */ 302 #define CONFIG_HARD_SPI 303 304 #define CONFIG_SF_DEFAULT_SPEED 10000000 305 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 306 307 #if defined(CONFIG_PCI) 308 /* 309 * General PCI 310 * Memory space is mapped 1-1, but I/O space must start from 0. 311 */ 312 313 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 314 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 315 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 316 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 317 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 318 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 319 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 320 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 321 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 322 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 323 324 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 325 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 326 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 327 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 328 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 329 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 330 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 331 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 332 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 333 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 334 335 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 336 #endif /* CONFIG_PCI */ 337 338 /* 339 * Environment 340 */ 341 #ifdef CONFIG_ENV_FIT_UCBOOT 342 343 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 344 #define CONFIG_ENV_SIZE 0x20000 345 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 346 347 #else 348 349 #define CONFIG_ENV_SPI_BUS 0 350 #define CONFIG_ENV_SPI_CS 0 351 #define CONFIG_ENV_SPI_MAX_HZ 10000000 352 #define CONFIG_ENV_SPI_MODE 0 353 354 #ifdef CONFIG_RAMBOOT_SPIFLASH 355 356 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 357 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 358 #define CONFIG_ENV_SECT_SIZE 0x1000 359 360 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 361 /* Address and size of Redundant Environment Sector */ 362 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 363 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 364 #endif 365 366 #elif defined(CONFIG_RAMBOOT_SDCARD) 367 #define CONFIG_FSL_FIXED_MMC_LOCATION 368 #define CONFIG_ENV_SIZE 0x2000 369 #define CONFIG_SYS_MMC_ENV_DEV 0 370 371 #elif defined(CONFIG_SYS_RAMBOOT) 372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 373 #define CONFIG_ENV_SIZE 0x2000 374 375 #else 376 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 377 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 378 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 379 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 380 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 381 /* Address and size of Redundant Environment Sector */ 382 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 383 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 384 #endif 385 386 #endif 387 388 #endif /* CONFIG_ENV_FIT_UCBOOT */ 389 390 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 391 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 392 393 /* 394 * USB 395 */ 396 #define CONFIG_HAS_FSL_DR_USB 397 398 #if defined(CONFIG_HAS_FSL_DR_USB) 399 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 400 401 #ifdef CONFIG_USB_EHCI_HCD 402 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 403 #define CONFIG_USB_EHCI_FSL 404 #endif 405 #endif 406 407 #undef CONFIG_WATCHDOG /* watchdog disabled */ 408 409 #ifdef CONFIG_MMC 410 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 411 #define CONFIG_MMC_SPI 412 #endif 413 414 /* Misc Extra Settings */ 415 #undef CONFIG_WATCHDOG /* watchdog disabled */ 416 417 /* 418 * Miscellaneous configurable options 419 */ 420 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 421 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 422 423 /* 424 * For booting Linux, the board info and command line data 425 * have to be in the first 64 MB of memory, since this is 426 * the maximum mapped by the Linux kernel during initialization. 427 */ 428 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 429 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 430 431 #if defined(CONFIG_CMD_KGDB) 432 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 433 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 434 #endif 435 436 /* 437 * Environment Configuration 438 */ 439 440 #if defined(CONFIG_TSEC_ENET) 441 442 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) 443 #else 444 #error "UCP1020 module revision is not defined !!!" 445 #endif 446 447 #define CONFIG_BOOTP_SERVERIP 448 449 #define CONFIG_MII /* MII PHY management */ 450 #define CONFIG_TSEC1_NAME "eTSEC1" 451 #define CONFIG_TSEC2_NAME "eTSEC2" 452 #define CONFIG_TSEC3_NAME "eTSEC3" 453 454 #define TSEC1_PHY_ADDR 4 455 #define TSEC2_PHY_ADDR 0 456 #define TSEC2_PHY_ADDR_SGMII 0x00 457 #define TSEC3_PHY_ADDR 6 458 459 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 460 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 461 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 462 463 #define TSEC1_PHYIDX 0 464 #define TSEC2_PHYIDX 0 465 #define TSEC3_PHYIDX 0 466 467 #endif 468 469 #define CONFIG_HOSTNAME "UCP1020" 470 #define CONFIG_ROOTPATH "/opt/nfsroot" 471 #define CONFIG_BOOTFILE "uImage" 472 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 473 474 /* default location for tftp and bootm */ 475 #define CONFIG_LOADADDR 1000000 476 477 #if defined(CONFIG_DONGLE) 478 479 #define CONFIG_EXTRA_ENV_SETTINGS \ 480 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 481 "bootfile=uImage\0" \ 482 "consoledev=ttyS0\0" \ 483 "cramfsfile=image.cramfs\0" \ 484 "dtbaddr=0x00c00000\0" \ 485 "dtbfile=image.dtb\0" \ 486 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 487 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 488 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 489 "fileaddr=0x01000000\0" \ 490 "filesize=0x00080000\0" \ 491 "flashmbr=sf probe 0; " \ 492 "tftp $loadaddr $mbr; " \ 493 "sf erase $mbr_offset +$filesize; " \ 494 "sf write $loadaddr $mbr_offset $filesize\0" \ 495 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 496 "protect off $nor_recoveryaddr +$filesize; " \ 497 "erase $nor_recoveryaddr +$filesize; " \ 498 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 499 "protect on $nor_recoveryaddr +$filesize\0 " \ 500 "flashuboot=tftp $ubootaddr $ubootfile; " \ 501 "protect off $nor_ubootaddr +$filesize; " \ 502 "erase $nor_ubootaddr +$filesize; " \ 503 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 504 "protect on $nor_ubootaddr +$filesize\0 " \ 505 "flashworking=tftp $workingaddr $cramfsfile; " \ 506 "protect off $nor_workingaddr +$filesize; " \ 507 "erase $nor_workingaddr +$filesize; " \ 508 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 509 "protect on $nor_workingaddr +$filesize\0 " \ 510 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 511 "kerneladdr=0x01100000\0" \ 512 "kernelfile=uImage\0" \ 513 "loadaddr=0x01000000\0" \ 514 "mbr=uCP1020d.mbr\0" \ 515 "mbr_offset=0x00000000\0" \ 516 "mmbr=uCP1020Quiet.mbr\0" \ 517 "mmcpart=0:2\0" \ 518 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 519 "mmc erase 1 1; " \ 520 "mmc write $loadaddr 1 1\0" \ 521 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 522 "mmc erase 0x40 0x400; " \ 523 "mmc write $loadaddr 0x40 0x400\0" \ 524 "netdev=eth0\0" \ 525 "nor_recoveryaddr=0xEC0A0000\0" \ 526 "nor_ubootaddr=0xEFF80000\0" \ 527 "nor_workingaddr=0xECFA0000\0" \ 528 "norbootrecovery=setenv bootargs $recoverybootargs" \ 529 " console=$consoledev,$baudrate $othbootargs; " \ 530 "run norloadrecovery; " \ 531 "bootm $kerneladdr - $dtbaddr\0" \ 532 "norbootworking=setenv bootargs $workingbootargs" \ 533 " console=$consoledev,$baudrate $othbootargs; " \ 534 "run norloadworking; " \ 535 "bootm $kerneladdr - $dtbaddr\0" \ 536 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 537 "setenv cramfsaddr $nor_recoveryaddr; " \ 538 "cramfsload $dtbaddr $dtbfile; " \ 539 "cramfsload $kerneladdr $kernelfile\0" \ 540 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 541 "setenv cramfsaddr $nor_workingaddr; " \ 542 "cramfsload $dtbaddr $dtbfile; " \ 543 "cramfsload $kerneladdr $kernelfile\0" \ 544 "prog_spi_mbr=run spi__mbr\0" \ 545 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 546 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 547 "run spi__cramfs\0" \ 548 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 549 " console=$consoledev,$baudrate $othbootargs; " \ 550 "tftp $rootfsaddr $rootfsfile; " \ 551 "tftp $loadaddr $kernelfile; " \ 552 "tftp $dtbaddr $dtbfile; " \ 553 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 554 "ramdisk_size=120000\0" \ 555 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 556 "recoveryaddr=0x02F00000\0" \ 557 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 558 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 559 "mw.l 0xffe0f008 0x00400000\0" \ 560 "rootfsaddr=0x02F00000\0" \ 561 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 562 "rootpath=/opt/nfsroot\0" \ 563 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 564 "protect off 0xeC000000 +$filesize; " \ 565 "erase 0xEC000000 +$filesize; " \ 566 "cp.b $loadaddr 0xEC000000 $filesize; " \ 567 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 568 "protect on 0xeC000000 +$filesize\0" \ 569 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 570 "protect off 0xeFF80000 +$filesize; " \ 571 "erase 0xEFF80000 +$filesize; " \ 572 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 573 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 574 "protect on 0xeFF80000 +$filesize\0" \ 575 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 576 "sf probe 0; sf erase 0x8000 +$filesize; " \ 577 "sf write $loadaddr 0x8000 $filesize\0" \ 578 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 579 "protect off 0xec0a0000 +$filesize; " \ 580 "erase 0xeC0A0000 +$filesize; " \ 581 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 582 "protect on 0xec0a0000 +$filesize\0" \ 583 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 584 "sf probe 1; sf erase 0 +$filesize; " \ 585 "sf write $loadaddr 0 $filesize\0" \ 586 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 587 "sf probe 0; sf erase 0 +$filesize; " \ 588 "sf write $loadaddr 0 $filesize\0" \ 589 "tftpflash=tftpboot $loadaddr $uboot; " \ 590 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 591 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 592 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 593 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 594 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 595 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 596 "ubootaddr=0x01000000\0" \ 597 "ubootfile=u-boot.bin\0" \ 598 "ubootd=u-boot4dongle.bin\0" \ 599 "upgrade=run flashworking\0" \ 600 "usb_phy_type=ulpi\0 " \ 601 "workingaddr=0x02F00000\0" \ 602 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 603 604 #else 605 606 #if defined(CONFIG_UCP1020T1) 607 608 #define CONFIG_EXTRA_ENV_SETTINGS \ 609 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 610 "bootfile=uImage\0" \ 611 "consoledev=ttyS0\0" \ 612 "cramfsfile=image.cramfs\0" \ 613 "dtbaddr=0x00c00000\0" \ 614 "dtbfile=image.dtb\0" \ 615 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 616 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 617 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 618 "fileaddr=0x01000000\0" \ 619 "filesize=0x00080000\0" \ 620 "flashmbr=sf probe 0; " \ 621 "tftp $loadaddr $mbr; " \ 622 "sf erase $mbr_offset +$filesize; " \ 623 "sf write $loadaddr $mbr_offset $filesize\0" \ 624 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 625 "protect off $nor_recoveryaddr +$filesize; " \ 626 "erase $nor_recoveryaddr +$filesize; " \ 627 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 628 "protect on $nor_recoveryaddr +$filesize\0 " \ 629 "flashuboot=tftp $ubootaddr $ubootfile; " \ 630 "protect off $nor_ubootaddr +$filesize; " \ 631 "erase $nor_ubootaddr +$filesize; " \ 632 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 633 "protect on $nor_ubootaddr +$filesize\0 " \ 634 "flashworking=tftp $workingaddr $cramfsfile; " \ 635 "protect off $nor_workingaddr +$filesize; " \ 636 "erase $nor_workingaddr +$filesize; " \ 637 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 638 "protect on $nor_workingaddr +$filesize\0 " \ 639 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 640 "kerneladdr=0x01100000\0" \ 641 "kernelfile=uImage\0" \ 642 "loadaddr=0x01000000\0" \ 643 "mbr=uCP1020.mbr\0" \ 644 "mbr_offset=0x00000000\0" \ 645 "netdev=eth0\0" \ 646 "nor_recoveryaddr=0xEC0A0000\0" \ 647 "nor_ubootaddr=0xEFF80000\0" \ 648 "nor_workingaddr=0xECFA0000\0" \ 649 "norbootrecovery=setenv bootargs $recoverybootargs" \ 650 " console=$consoledev,$baudrate $othbootargs; " \ 651 "run norloadrecovery; " \ 652 "bootm $kerneladdr - $dtbaddr\0" \ 653 "norbootworking=setenv bootargs $workingbootargs" \ 654 " console=$consoledev,$baudrate $othbootargs; " \ 655 "run norloadworking; " \ 656 "bootm $kerneladdr - $dtbaddr\0" \ 657 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 658 "setenv cramfsaddr $nor_recoveryaddr; " \ 659 "cramfsload $dtbaddr $dtbfile; " \ 660 "cramfsload $kerneladdr $kernelfile\0" \ 661 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 662 "setenv cramfsaddr $nor_workingaddr; " \ 663 "cramfsload $dtbaddr $dtbfile; " \ 664 "cramfsload $kerneladdr $kernelfile\0" \ 665 "othbootargs=quiet\0" \ 666 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 667 " console=$consoledev,$baudrate $othbootargs; " \ 668 "tftp $rootfsaddr $rootfsfile; " \ 669 "tftp $loadaddr $kernelfile; " \ 670 "tftp $dtbaddr $dtbfile; " \ 671 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 672 "ramdisk_size=120000\0" \ 673 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 674 "recoveryaddr=0x02F00000\0" \ 675 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 676 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 677 "mw.l 0xffe0f008 0x00400000\0" \ 678 "rootfsaddr=0x02F00000\0" \ 679 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 680 "rootpath=/opt/nfsroot\0" \ 681 "silent=1\0" \ 682 "tftpflash=tftpboot $loadaddr $uboot; " \ 683 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 684 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 685 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 686 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 687 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 688 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 689 "ubootaddr=0x01000000\0" \ 690 "ubootfile=u-boot.bin\0" \ 691 "upgrade=run flashworking\0" \ 692 "workingaddr=0x02F00000\0" \ 693 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 694 695 #else /* For Arcturus Modules */ 696 697 #define CONFIG_EXTRA_ENV_SETTINGS \ 698 "bootcmd=run norkernel\0" \ 699 "bootfile=uImage\0" \ 700 "consoledev=ttyS0\0" \ 701 "dtbaddr=0x00c00000\0" \ 702 "dtbfile=image.dtb\0" \ 703 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 704 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 705 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 706 "fileaddr=0x01000000\0" \ 707 "filesize=0x00080000\0" \ 708 "flashmbr=sf probe 0; " \ 709 "tftp $loadaddr $mbr; " \ 710 "sf erase $mbr_offset +$filesize; " \ 711 "sf write $loadaddr $mbr_offset $filesize\0" \ 712 "flashuboot=tftp $loadaddr $ubootfile; " \ 713 "protect off $nor_ubootaddr0 +$filesize; " \ 714 "erase $nor_ubootaddr0 +$filesize; " \ 715 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 716 "protect on $nor_ubootaddr0 +$filesize; " \ 717 "protect off $nor_ubootaddr1 +$filesize; " \ 718 "erase $nor_ubootaddr1 +$filesize; " \ 719 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 720 "protect on $nor_ubootaddr1 +$filesize\0 " \ 721 "format0=protect off $part0base +$part0size; " \ 722 "erase $part0base +$part0size\0" \ 723 "format1=protect off $part1base +$part1size; " \ 724 "erase $part1base +$part1size\0" \ 725 "format2=protect off $part2base +$part2size; " \ 726 "erase $part2base +$part2size\0" \ 727 "format3=protect off $part3base +$part3size; " \ 728 "erase $part3base +$part3size\0" \ 729 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 730 "kerneladdr=0x01100000\0" \ 731 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 732 "kernelfile=uImage\0" \ 733 "loadaddr=0x01000000\0" \ 734 "mbr=uCP1020.mbr\0" \ 735 "mbr_offset=0x00000000\0" \ 736 "netdev=eth0\0" \ 737 "nor_ubootaddr0=0xEC000000\0" \ 738 "nor_ubootaddr1=0xEFF80000\0" \ 739 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 740 "run norkernelload; " \ 741 "bootm $kerneladdr - $dtbaddr\0" \ 742 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 743 "setenv cramfsaddr $part0base; " \ 744 "cramfsload $dtbaddr $dtbfile; " \ 745 "cramfsload $kerneladdr $kernelfile\0" \ 746 "part0base=0xEC100000\0" \ 747 "part0size=0x00700000\0" \ 748 "part1base=0xEC800000\0" \ 749 "part1size=0x02000000\0" \ 750 "part2base=0xEE800000\0" \ 751 "part2size=0x00800000\0" \ 752 "part3base=0xEF000000\0" \ 753 "part3size=0x00F80000\0" \ 754 "partENVbase=0xEC080000\0" \ 755 "partENVsize=0x00080000\0" \ 756 "program0=tftp part0-000000.bin; " \ 757 "protect off $part0base +$filesize; " \ 758 "erase $part0base +$filesize; " \ 759 "cp.b $loadaddr $part0base $filesize; " \ 760 "echo Verifying...; " \ 761 "cmp.b $loadaddr $part0base $filesize\0" \ 762 "program1=tftp part1-000000.bin; " \ 763 "protect off $part1base +$filesize; " \ 764 "erase $part1base +$filesize; " \ 765 "cp.b $loadaddr $part1base $filesize; " \ 766 "echo Verifying...; " \ 767 "cmp.b $loadaddr $part1base $filesize\0" \ 768 "program2=tftp part2-000000.bin; " \ 769 "protect off $part2base +$filesize; " \ 770 "erase $part2base +$filesize; " \ 771 "cp.b $loadaddr $part2base $filesize; " \ 772 "echo Verifying...; " \ 773 "cmp.b $loadaddr $part2base $filesize\0" \ 774 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 775 " console=$consoledev,$baudrate $othbootargs; " \ 776 "tftp $rootfsaddr $rootfsfile; " \ 777 "tftp $loadaddr $kernelfile; " \ 778 "tftp $dtbaddr $dtbfile; " \ 779 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 780 "ramdisk_size=120000\0" \ 781 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 782 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 783 "mw.l 0xffe0f008 0x00400000\0" \ 784 "rootfsaddr=0x02F00000\0" \ 785 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 786 "rootpath=/opt/nfsroot\0" \ 787 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 788 "sf probe 0; sf erase 0 +$filesize; " \ 789 "sf write $loadaddr 0 $filesize\0" \ 790 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 791 "protect off 0xeC000000 +$filesize; " \ 792 "erase 0xEC000000 +$filesize; " \ 793 "cp.b $loadaddr 0xEC000000 $filesize; " \ 794 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 795 "protect on 0xeC000000 +$filesize\0" \ 796 "tftpflash=tftpboot $loadaddr $uboot; " \ 797 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 798 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 799 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 800 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 801 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 802 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 803 "ubootfile=u-boot.bin\0" \ 804 "upgrade=run flashuboot\0" \ 805 "usb_phy_type=ulpi\0 " \ 806 "boot_nfs= " \ 807 "setenv bootargs root=/dev/nfs rw " \ 808 "nfsroot=$serverip:$rootpath " \ 809 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "tftp $loadaddr $bootfile;" \ 812 "tftp $fdtaddr $fdtfile;" \ 813 "bootm $loadaddr - $fdtaddr\0" \ 814 "boot_hd = " \ 815 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "usb start;" \ 818 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 819 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 820 "bootm $loadaddr - $fdtaddr\0" \ 821 "boot_usb_fat = " \ 822 "setenv bootargs root=/dev/ram rw " \ 823 "console=$consoledev,$baudrate $othbootargs " \ 824 "ramdisk_size=$ramdisk_size;" \ 825 "usb start;" \ 826 "fatload usb 0:2 $loadaddr $bootfile;" \ 827 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 828 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 829 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 830 "boot_usb_ext2 = " \ 831 "setenv bootargs root=/dev/ram rw " \ 832 "console=$consoledev,$baudrate $othbootargs " \ 833 "ramdisk_size=$ramdisk_size;" \ 834 "usb start;" \ 835 "ext2load usb 0:4 $loadaddr $bootfile;" \ 836 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 837 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 838 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 839 "boot_nor = " \ 840 "setenv bootargs root=/dev/$jffs2nor rw " \ 841 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 842 "bootm $norbootaddr - $norfdtaddr\0 " \ 843 "boot_ram = " \ 844 "setenv bootargs root=/dev/ram rw " \ 845 "console=$consoledev,$baudrate $othbootargs " \ 846 "ramdisk_size=$ramdisk_size;" \ 847 "tftp $ramdiskaddr $ramdiskfile;" \ 848 "tftp $loadaddr $bootfile;" \ 849 "tftp $fdtaddr $fdtfile;" \ 850 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 851 852 #endif 853 #endif 854 855 #endif /* __CONFIG_H */ 856
