1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keithw (at) vmware.com> 30 */ 31 32 #ifndef BRW_EU_DEFINES_H 33 #define BRW_EU_DEFINES_H 34 35 #include "util/macros.h" 36 37 /* The following hunk, up-to "Execution Unit" is used by both the 38 * intel/compiler and i965 codebase. */ 39 40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) 41 /* Using the GNU statement expression extension */ 42 #define SET_FIELD(value, field) \ 43 ({ \ 44 uint32_t fieldval = (value) << field ## _SHIFT; \ 45 assert((fieldval & ~ field ## _MASK) == 0); \ 46 fieldval & field ## _MASK; \ 47 }) 48 49 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low)) 50 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 51 52 #define _3DPRIM_POINTLIST 0x01 53 #define _3DPRIM_LINELIST 0x02 54 #define _3DPRIM_LINESTRIP 0x03 55 #define _3DPRIM_TRILIST 0x04 56 #define _3DPRIM_TRISTRIP 0x05 57 #define _3DPRIM_TRIFAN 0x06 58 #define _3DPRIM_QUADLIST 0x07 59 #define _3DPRIM_QUADSTRIP 0x08 60 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */ 61 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */ 62 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */ 63 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */ 64 #define _3DPRIM_TRISTRIP_REVERSE 0x0D 65 #define _3DPRIM_POLYGON 0x0E 66 #define _3DPRIM_RECTLIST 0x0F 67 #define _3DPRIM_LINELOOP 0x10 68 #define _3DPRIM_POINTLIST_BF 0x11 69 #define _3DPRIM_LINESTRIP_CONT 0x12 70 #define _3DPRIM_LINESTRIP_BF 0x13 71 #define _3DPRIM_LINESTRIP_CONT_BF 0x14 72 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16 73 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); }) 74 75 /* Bitfields for the URB_WRITE message, DW2 of message header: */ 76 #define URB_WRITE_PRIM_END 0x1 77 #define URB_WRITE_PRIM_START 0x2 78 #define URB_WRITE_PRIM_TYPE_SHIFT 2 79 80 #define BRW_SPRITE_POINT_ENABLE 16 81 82 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0 83 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1 84 85 /* Execution Unit (EU) defines 86 */ 87 88 #define BRW_ALIGN_1 0 89 #define BRW_ALIGN_16 1 90 91 #define BRW_ADDRESS_DIRECT 0 92 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 93 94 #define BRW_CHANNEL_X 0 95 #define BRW_CHANNEL_Y 1 96 #define BRW_CHANNEL_Z 2 97 #define BRW_CHANNEL_W 3 98 99 enum brw_compression { 100 BRW_COMPRESSION_NONE = 0, 101 BRW_COMPRESSION_2NDHALF = 1, 102 BRW_COMPRESSION_COMPRESSED = 2, 103 }; 104 105 #define GEN6_COMPRESSION_1Q 0 106 #define GEN6_COMPRESSION_2Q 1 107 #define GEN6_COMPRESSION_3Q 2 108 #define GEN6_COMPRESSION_4Q 3 109 #define GEN6_COMPRESSION_1H 0 110 #define GEN6_COMPRESSION_2H 2 111 112 enum PACKED brw_conditional_mod { 113 BRW_CONDITIONAL_NONE = 0, 114 BRW_CONDITIONAL_Z = 1, 115 BRW_CONDITIONAL_NZ = 2, 116 BRW_CONDITIONAL_EQ = 1, /* Z */ 117 BRW_CONDITIONAL_NEQ = 2, /* NZ */ 118 BRW_CONDITIONAL_G = 3, 119 BRW_CONDITIONAL_GE = 4, 120 BRW_CONDITIONAL_L = 5, 121 BRW_CONDITIONAL_LE = 6, 122 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */ 123 BRW_CONDITIONAL_O = 8, 124 BRW_CONDITIONAL_U = 9, 125 }; 126 127 #define BRW_DEBUG_NONE 0 128 #define BRW_DEBUG_BREAKPOINT 1 129 130 #define BRW_DEPENDENCY_NORMAL 0 131 #define BRW_DEPENDENCY_NOTCLEARED 1 132 #define BRW_DEPENDENCY_NOTCHECKED 2 133 #define BRW_DEPENDENCY_DISABLE 3 134 135 enum PACKED brw_execution_size { 136 BRW_EXECUTE_1 = 0, 137 BRW_EXECUTE_2 = 1, 138 BRW_EXECUTE_4 = 2, 139 BRW_EXECUTE_8 = 3, 140 BRW_EXECUTE_16 = 4, 141 BRW_EXECUTE_32 = 5, 142 }; 143 144 enum PACKED brw_horizontal_stride { 145 BRW_HORIZONTAL_STRIDE_0 = 0, 146 BRW_HORIZONTAL_STRIDE_1 = 1, 147 BRW_HORIZONTAL_STRIDE_2 = 2, 148 BRW_HORIZONTAL_STRIDE_4 = 3, 149 }; 150 151 enum PACKED gen10_align1_3src_src_horizontal_stride { 152 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0, 153 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1, 154 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2, 155 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3, 156 }; 157 158 enum PACKED gen10_align1_3src_dst_horizontal_stride { 159 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0, 160 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1, 161 }; 162 163 #define BRW_INSTRUCTION_NORMAL 0 164 #define BRW_INSTRUCTION_SATURATE 1 165 166 #define BRW_MASK_ENABLE 0 167 #define BRW_MASK_DISABLE 1 168 169 /** @{ 170 * 171 * Gen6 has replaced "mask enable/disable" with WECtrl, which is 172 * effectively the same but much simpler to think about. Now, there 173 * are two contributors ANDed together to whether channels are 174 * executed: The predication on the instruction, and the channel write 175 * enable. 176 */ 177 /** 178 * This is the default value. It means that a channel's write enable is set 179 * if the per-channel IP is pointing at this instruction. 180 */ 181 #define BRW_WE_NORMAL 0 182 /** 183 * This is used like BRW_MASK_DISABLE, and causes all channels to have 184 * their write enable set. Note that predication still contributes to 185 * whether the channel actually gets written. 186 */ 187 #define BRW_WE_ALL 1 188 /** @} */ 189 190 enum opcode { 191 /* These are the actual hardware opcodes. */ 192 BRW_OPCODE_ILLEGAL = 0, 193 BRW_OPCODE_MOV = 1, 194 BRW_OPCODE_SEL = 2, 195 BRW_OPCODE_MOVI = 3, /**< G45+ */ 196 BRW_OPCODE_NOT = 4, 197 BRW_OPCODE_AND = 5, 198 BRW_OPCODE_OR = 6, 199 BRW_OPCODE_XOR = 7, 200 BRW_OPCODE_SHR = 8, 201 BRW_OPCODE_SHL = 9, 202 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */ 203 // BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */ 204 /* Reserved - 11 */ 205 BRW_OPCODE_ASR = 12, 206 /* Reserved - 13-15 */ 207 BRW_OPCODE_CMP = 16, 208 BRW_OPCODE_CMPN = 17, 209 BRW_OPCODE_CSEL = 18, /**< Gen8+ */ 210 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */ 211 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */ 212 /* Reserved - 21-22 */ 213 BRW_OPCODE_BFREV = 23, /**< Gen7+ */ 214 BRW_OPCODE_BFE = 24, /**< Gen7+ */ 215 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */ 216 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */ 217 /* Reserved - 27-31 */ 218 BRW_OPCODE_JMPI = 32, 219 // BRW_OPCODE_BRD = 33, /**< Gen7+ */ 220 BRW_OPCODE_IF = 34, 221 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */ 222 // BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */ 223 BRW_OPCODE_ELSE = 36, 224 BRW_OPCODE_ENDIF = 37, 225 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */ 226 // BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */ 227 BRW_OPCODE_WHILE = 39, 228 BRW_OPCODE_BREAK = 40, 229 BRW_OPCODE_CONTINUE = 41, 230 BRW_OPCODE_HALT = 42, 231 // BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */ 232 // BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */ 233 // BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */ 234 // BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */ 235 // BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */ 236 // BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */ 237 // BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */ 238 // BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */ 239 // BRW_OPCODE_POP = 47, /**< Pre-Gen6 */ 240 BRW_OPCODE_WAIT = 48, 241 BRW_OPCODE_SEND = 49, 242 BRW_OPCODE_SENDC = 50, 243 BRW_OPCODE_SENDS = 51, /**< Gen9+ */ 244 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */ 245 /* Reserved 53-55 */ 246 BRW_OPCODE_MATH = 56, /**< Gen6+ */ 247 /* Reserved 57-63 */ 248 BRW_OPCODE_ADD = 64, 249 BRW_OPCODE_MUL = 65, 250 BRW_OPCODE_AVG = 66, 251 BRW_OPCODE_FRC = 67, 252 BRW_OPCODE_RNDU = 68, 253 BRW_OPCODE_RNDD = 69, 254 BRW_OPCODE_RNDE = 70, 255 BRW_OPCODE_RNDZ = 71, 256 BRW_OPCODE_MAC = 72, 257 BRW_OPCODE_MACH = 73, 258 BRW_OPCODE_LZD = 74, 259 BRW_OPCODE_FBH = 75, /**< Gen7+ */ 260 BRW_OPCODE_FBL = 76, /**< Gen7+ */ 261 BRW_OPCODE_CBIT = 77, /**< Gen7+ */ 262 BRW_OPCODE_ADDC = 78, /**< Gen7+ */ 263 BRW_OPCODE_SUBB = 79, /**< Gen7+ */ 264 BRW_OPCODE_SAD2 = 80, 265 BRW_OPCODE_SADA2 = 81, 266 /* Reserved 82-83 */ 267 BRW_OPCODE_DP4 = 84, 268 BRW_OPCODE_DPH = 85, 269 BRW_OPCODE_DP3 = 86, 270 BRW_OPCODE_DP2 = 87, 271 /* Reserved 88 */ 272 BRW_OPCODE_LINE = 89, 273 BRW_OPCODE_PLN = 90, /**< G45+ */ 274 BRW_OPCODE_MAD = 91, /**< Gen6+ */ 275 BRW_OPCODE_LRP = 92, /**< Gen6+ */ 276 // BRW_OPCODE_MADM = 93, /**< Gen8+ */ 277 /* Reserved 94-124 */ 278 BRW_OPCODE_NENOP = 125, /**< G45 only */ 279 BRW_OPCODE_NOP = 126, 280 /* Reserved 127 */ 281 282 /* These are compiler backend opcodes that get translated into other 283 * instructions. 284 */ 285 FS_OPCODE_FB_WRITE = 128, 286 287 /** 288 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as 289 * individual sources instead of as a single payload blob. The 290 * position/ordering of the arguments are defined by the enum 291 * fb_write_logical_srcs. 292 */ 293 FS_OPCODE_FB_WRITE_LOGICAL, 294 295 FS_OPCODE_REP_FB_WRITE, 296 297 FS_OPCODE_FB_READ, 298 FS_OPCODE_FB_READ_LOGICAL, 299 300 SHADER_OPCODE_RCP, 301 SHADER_OPCODE_RSQ, 302 SHADER_OPCODE_SQRT, 303 SHADER_OPCODE_EXP2, 304 SHADER_OPCODE_LOG2, 305 SHADER_OPCODE_POW, 306 SHADER_OPCODE_INT_QUOTIENT, 307 SHADER_OPCODE_INT_REMAINDER, 308 SHADER_OPCODE_SIN, 309 SHADER_OPCODE_COS, 310 311 /** 312 * Texture sampling opcodes. 313 * 314 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 315 * opcode but instead of taking a single payload blob they expect their 316 * arguments separately as individual sources. The position/ordering of the 317 * arguments are defined by the enum tex_logical_srcs. 318 */ 319 SHADER_OPCODE_TEX, 320 SHADER_OPCODE_TEX_LOGICAL, 321 SHADER_OPCODE_TXD, 322 SHADER_OPCODE_TXD_LOGICAL, 323 SHADER_OPCODE_TXF, 324 SHADER_OPCODE_TXF_LOGICAL, 325 SHADER_OPCODE_TXF_LZ, 326 SHADER_OPCODE_TXL, 327 SHADER_OPCODE_TXL_LOGICAL, 328 SHADER_OPCODE_TXL_LZ, 329 SHADER_OPCODE_TXS, 330 SHADER_OPCODE_TXS_LOGICAL, 331 FS_OPCODE_TXB, 332 FS_OPCODE_TXB_LOGICAL, 333 SHADER_OPCODE_TXF_CMS, 334 SHADER_OPCODE_TXF_CMS_LOGICAL, 335 SHADER_OPCODE_TXF_CMS_W, 336 SHADER_OPCODE_TXF_CMS_W_LOGICAL, 337 SHADER_OPCODE_TXF_UMS, 338 SHADER_OPCODE_TXF_UMS_LOGICAL, 339 SHADER_OPCODE_TXF_MCS, 340 SHADER_OPCODE_TXF_MCS_LOGICAL, 341 SHADER_OPCODE_LOD, 342 SHADER_OPCODE_LOD_LOGICAL, 343 SHADER_OPCODE_TG4, 344 SHADER_OPCODE_TG4_LOGICAL, 345 SHADER_OPCODE_TG4_OFFSET, 346 SHADER_OPCODE_TG4_OFFSET_LOGICAL, 347 SHADER_OPCODE_SAMPLEINFO, 348 SHADER_OPCODE_SAMPLEINFO_LOGICAL, 349 350 /** 351 * Combines multiple sources of size 1 into a larger virtual GRF. 352 * For example, parameters for a send-from-GRF message. Or, updating 353 * channels of a size 4 VGRF used to store vec4s such as texturing results. 354 * 355 * This will be lowered into MOVs from each source to consecutive offsets 356 * of the destination VGRF. 357 * 358 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV, 359 * but still reserves the first channel of the destination VGRF. This can be 360 * used to reserve space for, say, a message header set up by the generators. 361 */ 362 SHADER_OPCODE_LOAD_PAYLOAD, 363 364 /** 365 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this 366 * acts intra-channel, obtaining the final value for each channel by 367 * combining the sources values for the same channel, the first source 368 * occupying the lowest bits and the last source occupying the highest 369 * bits. 370 */ 371 FS_OPCODE_PACK, 372 373 SHADER_OPCODE_SHADER_TIME_ADD, 374 375 /** 376 * Typed and untyped surface access opcodes. 377 * 378 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 379 * opcode but instead of taking a single payload blob they expect their 380 * arguments separately as individual sources: 381 * 382 * Source 0: [required] Surface coordinates. 383 * Source 1: [optional] Operation source. 384 * Source 2: [required] Surface index. 385 * Source 3: [required] Number of coordinate components (as UD immediate). 386 * Source 4: [required] Opcode-specific control immediate, same as source 2 387 * of the matching non-LOGICAL opcode. 388 */ 389 SHADER_OPCODE_UNTYPED_ATOMIC, 390 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, 391 SHADER_OPCODE_UNTYPED_SURFACE_READ, 392 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, 393 SHADER_OPCODE_UNTYPED_SURFACE_WRITE, 394 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, 395 396 SHADER_OPCODE_TYPED_ATOMIC, 397 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, 398 SHADER_OPCODE_TYPED_SURFACE_READ, 399 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, 400 SHADER_OPCODE_TYPED_SURFACE_WRITE, 401 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, 402 403 SHADER_OPCODE_RND_MODE, 404 405 /** 406 * Byte scattered write/read opcodes. 407 * 408 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 409 * opcode, but instead of taking a single payload blog they expect their 410 * arguments separately as individual sources, like untyped write/read. 411 */ 412 SHADER_OPCODE_BYTE_SCATTERED_READ, 413 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, 414 SHADER_OPCODE_BYTE_SCATTERED_WRITE, 415 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, 416 417 SHADER_OPCODE_MEMORY_FENCE, 418 419 SHADER_OPCODE_GEN4_SCRATCH_READ, 420 SHADER_OPCODE_GEN4_SCRATCH_WRITE, 421 SHADER_OPCODE_GEN7_SCRATCH_READ, 422 423 /** 424 * Gen8+ SIMD8 URB Read messages. 425 */ 426 SHADER_OPCODE_URB_READ_SIMD8, 427 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, 428 429 SHADER_OPCODE_URB_WRITE_SIMD8, 430 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT, 431 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, 432 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT, 433 434 /** 435 * Return the index of an arbitrary live channel (i.e. one of the channels 436 * enabled in the current execution mask) and assign it to the first 437 * component of the destination. Expected to be used as input for the 438 * BROADCAST pseudo-opcode. 439 */ 440 SHADER_OPCODE_FIND_LIVE_CHANNEL, 441 442 /** 443 * Pick the channel from its first source register given by the index 444 * specified as second source. Useful for variable indexing of surfaces. 445 * 446 * Note that because the result of this instruction is by definition 447 * uniform and it can always be splatted to multiple channels using a 448 * scalar regioning mode, only the first channel of the destination region 449 * is guaranteed to be updated, which implies that BROADCAST instructions 450 * should usually be marked force_writemask_all. 451 */ 452 SHADER_OPCODE_BROADCAST, 453 454 SHADER_OPCODE_GET_BUFFER_SIZE, 455 456 VEC4_OPCODE_MOV_BYTES, 457 VEC4_OPCODE_PACK_BYTES, 458 VEC4_OPCODE_UNPACK_UNIFORM, 459 VEC4_OPCODE_DOUBLE_TO_F32, 460 VEC4_OPCODE_DOUBLE_TO_D32, 461 VEC4_OPCODE_DOUBLE_TO_U32, 462 VEC4_OPCODE_TO_DOUBLE, 463 VEC4_OPCODE_PICK_LOW_32BIT, 464 VEC4_OPCODE_PICK_HIGH_32BIT, 465 VEC4_OPCODE_SET_LOW_32BIT, 466 VEC4_OPCODE_SET_HIGH_32BIT, 467 468 FS_OPCODE_DDX_COARSE, 469 FS_OPCODE_DDX_FINE, 470 /** 471 * Compute dFdy(), dFdyCoarse(), or dFdyFine(). 472 */ 473 FS_OPCODE_DDY_COARSE, 474 FS_OPCODE_DDY_FINE, 475 FS_OPCODE_CINTERP, 476 FS_OPCODE_LINTERP, 477 FS_OPCODE_PIXEL_X, 478 FS_OPCODE_PIXEL_Y, 479 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 480 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7, 481 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4, 482 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7, 483 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, 484 FS_OPCODE_MOV_DISPATCH_TO_FLAGS, 485 FS_OPCODE_DISCARD_JUMP, 486 FS_OPCODE_SET_SAMPLE_ID, 487 FS_OPCODE_PACK_HALF_2x16_SPLIT, 488 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, 489 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, 490 FS_OPCODE_PLACEHOLDER_HALT, 491 FS_OPCODE_INTERPOLATE_AT_SAMPLE, 492 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, 493 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, 494 495 VS_OPCODE_URB_WRITE, 496 VS_OPCODE_PULL_CONSTANT_LOAD, 497 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7, 498 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9, 499 500 VS_OPCODE_UNPACK_FLAGS_SIMD4X2, 501 502 /** 503 * Write geometry shader output data to the URB. 504 * 505 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from 506 * R0 to the first MRF. This allows the geometry shader to override the 507 * "Slot {0,1} Offset" fields in the message header. 508 */ 509 GS_OPCODE_URB_WRITE, 510 511 /** 512 * Write geometry shader output data to the URB and request a new URB 513 * handle (gen6). 514 * 515 * This opcode doesn't do an implied move from R0 to the first MRF. 516 */ 517 GS_OPCODE_URB_WRITE_ALLOCATE, 518 519 /** 520 * Terminate the geometry shader thread by doing an empty URB write. 521 * 522 * This opcode doesn't do an implied move from R0 to the first MRF. This 523 * allows the geometry shader to override the "GS Number of Output Vertices 524 * for Slot {0,1}" fields in the message header. 525 */ 526 GS_OPCODE_THREAD_END, 527 528 /** 529 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header. 530 * 531 * - dst is the MRF containing the message header. 532 * 533 * - src0.x indicates which portion of the URB should be written to (e.g. a 534 * vertex number) 535 * 536 * - src1 is an immediate multiplier which will be applied to src0 537 * (e.g. the size of a single vertex in the URB). 538 * 539 * Note: the hardware will apply this offset *in addition to* the offset in 540 * vec4_instruction::offset. 541 */ 542 GS_OPCODE_SET_WRITE_OFFSET, 543 544 /** 545 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a 546 * URB_WRITE message header. 547 * 548 * - dst is the MRF containing the message header. 549 * 550 * - src0.x is the vertex count. The upper 16 bits will be ignored. 551 */ 552 GS_OPCODE_SET_VERTEX_COUNT, 553 554 /** 555 * Set DWORD 2 of dst to the value in src. 556 */ 557 GS_OPCODE_SET_DWORD_2, 558 559 /** 560 * Prepare the dst register for storage in the "Channel Mask" fields of a 561 * URB_WRITE message header. 562 * 563 * DWORD 4 of dst is shifted left by 4 bits, so that later, 564 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the 565 * final channel mask. 566 * 567 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to 568 * form the final channel mask, DWORDs 0 and 4 of the dst register must not 569 * have any extraneous bits set prior to execution of this opcode (that is, 570 * they should be in the range 0x0 to 0xf). 571 */ 572 GS_OPCODE_PREPARE_CHANNEL_MASKS, 573 574 /** 575 * Set the "Channel Mask" fields of a URB_WRITE message header. 576 * 577 * - dst is the MRF containing the message header. 578 * 579 * - src.x is the channel mask, as prepared by 580 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to 581 * form the final channel mask. 582 */ 583 GS_OPCODE_SET_CHANNEL_MASKS, 584 585 /** 586 * Get the "Instance ID" fields from the payload. 587 * 588 * - dst is the GRF for gl_InvocationID. 589 */ 590 GS_OPCODE_GET_INSTANCE_ID, 591 592 /** 593 * Send a FF_SYNC message to allocate initial URB handles (gen6). 594 * 595 * - dst will be used as the writeback register for the FF_SYNC operation. 596 * 597 * - src0 is the number of primitives written. 598 * 599 * - src1 is the value to hold in M0.0: number of SO vertices to write 600 * and number of SO primitives needed. Its value will be overwritten 601 * with the SVBI values if transform feedback is enabled. 602 * 603 * Note: This opcode uses an implicit MRF register for the ff_sync message 604 * header, so the caller is expected to set inst->base_mrf and initialize 605 * that MRF register to r0. This opcode will also write to this MRF register 606 * to include the allocated URB handle so it can then be reused directly as 607 * the header in the URB write operation we are allocating the handle for. 608 */ 609 GS_OPCODE_FF_SYNC, 610 611 /** 612 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate 613 * register. 614 * 615 * - dst is the GRF where PrimitiveID information will be moved. 616 */ 617 GS_OPCODE_SET_PRIMITIVE_ID, 618 619 /** 620 * Write transform feedback data to the SVB by sending a SVB WRITE message. 621 * Used in gen6. 622 * 623 * - dst is the MRF register containing the message header. 624 * 625 * - src0 is the register where the vertex data is going to be copied from. 626 * 627 * - src1 is the destination register when write commit occurs. 628 */ 629 GS_OPCODE_SVB_WRITE, 630 631 /** 632 * Set destination index in the SVB write message payload (M0.5). Used 633 * in gen6 for transform feedback. 634 * 635 * - dst is the header to save the destination indices for SVB WRITE. 636 * - src is the register that holds the destination indices value. 637 */ 638 GS_OPCODE_SVB_SET_DST_INDEX, 639 640 /** 641 * Prepare Mx.0 subregister for being used in the FF_SYNC message header. 642 * Used in gen6 for transform feedback. 643 * 644 * - dst will hold the register with the final Mx.0 value. 645 * 646 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite) 647 * 648 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded) 649 * 650 * - src2 is the value to hold in M0: number of SO vertices to write 651 * and number of SO primitives needed. 652 */ 653 GS_OPCODE_FF_SYNC_SET_PRIMITIVES, 654 655 /** 656 * Terminate the compute shader. 657 */ 658 CS_OPCODE_CS_TERMINATE, 659 660 /** 661 * GLSL barrier() 662 */ 663 SHADER_OPCODE_BARRIER, 664 665 /** 666 * Calculate the high 32-bits of a 32x32 multiply. 667 */ 668 SHADER_OPCODE_MULH, 669 670 /** 671 * A MOV that uses VxH indirect addressing. 672 * 673 * Source 0: A register to start from (HW_REG). 674 * Source 1: An indirect offset (in bytes, UD GRF). 675 * Source 2: The length of the region that could be accessed (in bytes, 676 * UD immediate). 677 */ 678 SHADER_OPCODE_MOV_INDIRECT, 679 680 VEC4_OPCODE_URB_READ, 681 TCS_OPCODE_GET_INSTANCE_ID, 682 TCS_OPCODE_URB_WRITE, 683 TCS_OPCODE_SET_INPUT_URB_OFFSETS, 684 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, 685 TCS_OPCODE_GET_PRIMITIVE_ID, 686 TCS_OPCODE_CREATE_BARRIER_HEADER, 687 TCS_OPCODE_SRC0_010_IS_ZERO, 688 TCS_OPCODE_RELEASE_INPUT, 689 TCS_OPCODE_THREAD_END, 690 691 TES_OPCODE_GET_PRIMITIVE_ID, 692 TES_OPCODE_CREATE_INPUT_READ_HEADER, 693 TES_OPCODE_ADD_INDIRECT_URB_OFFSET, 694 }; 695 696 enum brw_urb_write_flags { 697 BRW_URB_WRITE_NO_FLAGS = 0, 698 699 /** 700 * Causes a new URB entry to be allocated, and its address stored in the 701 * destination register (gen < 7). 702 */ 703 BRW_URB_WRITE_ALLOCATE = 0x1, 704 705 /** 706 * Causes the current URB entry to be deallocated (gen < 7). 707 */ 708 BRW_URB_WRITE_UNUSED = 0x2, 709 710 /** 711 * Causes the thread to terminate. 712 */ 713 BRW_URB_WRITE_EOT = 0x4, 714 715 /** 716 * Indicates that the given URB entry is complete, and may be sent further 717 * down the 3D pipeline (gen < 7). 718 */ 719 BRW_URB_WRITE_COMPLETE = 0x8, 720 721 /** 722 * Indicates that an additional offset (which may be different for the two 723 * vec4 slots) is stored in the message header (gen == 7). 724 */ 725 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10, 726 727 /** 728 * Indicates that the channel masks in the URB_WRITE message header should 729 * not be overridden to 0xff (gen == 7). 730 */ 731 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20, 732 733 /** 734 * Indicates that the data should be sent to the URB using the 735 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This 736 * causes offsets to be interpreted as multiples of an OWORD instead of an 737 * HWORD, and only allows one OWORD to be written. 738 */ 739 BRW_URB_WRITE_OWORD = 0x40, 740 741 /** 742 * Convenient combination of flags: end the thread while simultaneously 743 * marking the given URB entry as complete. 744 */ 745 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE, 746 747 /** 748 * Convenient combination of flags: mark the given URB entry as complete 749 * and simultaneously allocate a new one. 750 */ 751 BRW_URB_WRITE_ALLOCATE_COMPLETE = 752 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE, 753 }; 754 755 enum fb_write_logical_srcs { 756 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */ 757 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */ 758 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA, 759 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */ 760 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */ 761 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */ 762 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */ 763 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */ 764 FB_WRITE_LOGICAL_NUM_SRCS 765 }; 766 767 enum tex_logical_srcs { 768 /** Texture coordinates */ 769 TEX_LOGICAL_SRC_COORDINATE, 770 /** Shadow comparator */ 771 TEX_LOGICAL_SRC_SHADOW_C, 772 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */ 773 TEX_LOGICAL_SRC_LOD, 774 /** dPdy if the operation takes explicit derivatives */ 775 TEX_LOGICAL_SRC_LOD2, 776 /** Sample index */ 777 TEX_LOGICAL_SRC_SAMPLE_INDEX, 778 /** MCS data */ 779 TEX_LOGICAL_SRC_MCS, 780 /** REQUIRED: Texture surface index */ 781 TEX_LOGICAL_SRC_SURFACE, 782 /** Texture sampler index */ 783 TEX_LOGICAL_SRC_SAMPLER, 784 /** Texel offset for gathers */ 785 TEX_LOGICAL_SRC_TG4_OFFSET, 786 /** REQUIRED: Number of coordinate components (as UD immediate) */ 787 TEX_LOGICAL_SRC_COORD_COMPONENTS, 788 /** REQUIRED: Number of derivative components (as UD immediate) */ 789 TEX_LOGICAL_SRC_GRAD_COMPONENTS, 790 791 TEX_LOGICAL_NUM_SRCS, 792 }; 793 794 #ifdef __cplusplus 795 /** 796 * Allow brw_urb_write_flags enums to be ORed together. 797 */ 798 inline brw_urb_write_flags 799 operator|(brw_urb_write_flags x, brw_urb_write_flags y) 800 { 801 return static_cast<brw_urb_write_flags>(static_cast<int>(x) | 802 static_cast<int>(y)); 803 } 804 #endif 805 806 enum PACKED brw_predicate { 807 BRW_PREDICATE_NONE = 0, 808 BRW_PREDICATE_NORMAL = 1, 809 BRW_PREDICATE_ALIGN1_ANYV = 2, 810 BRW_PREDICATE_ALIGN1_ALLV = 3, 811 BRW_PREDICATE_ALIGN1_ANY2H = 4, 812 BRW_PREDICATE_ALIGN1_ALL2H = 5, 813 BRW_PREDICATE_ALIGN1_ANY4H = 6, 814 BRW_PREDICATE_ALIGN1_ALL4H = 7, 815 BRW_PREDICATE_ALIGN1_ANY8H = 8, 816 BRW_PREDICATE_ALIGN1_ALL8H = 9, 817 BRW_PREDICATE_ALIGN1_ANY16H = 10, 818 BRW_PREDICATE_ALIGN1_ALL16H = 11, 819 BRW_PREDICATE_ALIGN1_ANY32H = 12, 820 BRW_PREDICATE_ALIGN1_ALL32H = 13, 821 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2, 822 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3, 823 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4, 824 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5, 825 BRW_PREDICATE_ALIGN16_ANY4H = 6, 826 BRW_PREDICATE_ALIGN16_ALL4H = 7, 827 }; 828 829 enum PACKED brw_reg_file { 830 BRW_ARCHITECTURE_REGISTER_FILE = 0, 831 BRW_GENERAL_REGISTER_FILE = 1, 832 BRW_MESSAGE_REGISTER_FILE = 2, 833 BRW_IMMEDIATE_VALUE = 3, 834 835 ARF = BRW_ARCHITECTURE_REGISTER_FILE, 836 FIXED_GRF = BRW_GENERAL_REGISTER_FILE, 837 MRF = BRW_MESSAGE_REGISTER_FILE, 838 IMM = BRW_IMMEDIATE_VALUE, 839 840 /* These are not hardware values */ 841 VGRF, 842 ATTR, 843 UNIFORM, /* prog_data->params[reg] */ 844 BAD_FILE, 845 }; 846 847 enum PACKED gen10_align1_3src_reg_file { 848 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0, 849 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */ 850 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ 851 }; 852 853 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction 854 * word is "Execution Datatype" which controls whether the instruction operates 855 * on float or integer types. The register arguments have fields that offer 856 * more fine control their respective types. 857 */ 858 enum PACKED gen10_align1_3src_exec_type { 859 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0, 860 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1, 861 }; 862 863 #define BRW_ARF_NULL 0x00 864 #define BRW_ARF_ADDRESS 0x10 865 #define BRW_ARF_ACCUMULATOR 0x20 866 #define BRW_ARF_FLAG 0x30 867 #define BRW_ARF_MASK 0x40 868 #define BRW_ARF_MASK_STACK 0x50 869 #define BRW_ARF_MASK_STACK_DEPTH 0x60 870 #define BRW_ARF_STATE 0x70 871 #define BRW_ARF_CONTROL 0x80 872 #define BRW_ARF_NOTIFICATION_COUNT 0x90 873 #define BRW_ARF_IP 0xA0 874 #define BRW_ARF_TDR 0xB0 875 #define BRW_ARF_TIMESTAMP 0xC0 876 877 #define BRW_MRF_COMPR4 (1 << 7) 878 879 #define BRW_AMASK 0 880 #define BRW_IMASK 1 881 #define BRW_LMASK 2 882 #define BRW_CMASK 3 883 884 885 886 #define BRW_THREAD_NORMAL 0 887 #define BRW_THREAD_ATOMIC 1 888 #define BRW_THREAD_SWITCH 2 889 890 enum PACKED brw_vertical_stride { 891 BRW_VERTICAL_STRIDE_0 = 0, 892 BRW_VERTICAL_STRIDE_1 = 1, 893 BRW_VERTICAL_STRIDE_2 = 2, 894 BRW_VERTICAL_STRIDE_4 = 3, 895 BRW_VERTICAL_STRIDE_8 = 4, 896 BRW_VERTICAL_STRIDE_16 = 5, 897 BRW_VERTICAL_STRIDE_32 = 6, 898 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF, 899 }; 900 901 enum PACKED gen10_align1_3src_vertical_stride { 902 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, 903 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, 904 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2, 905 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3, 906 }; 907 908 enum PACKED brw_width { 909 BRW_WIDTH_1 = 0, 910 BRW_WIDTH_2 = 1, 911 BRW_WIDTH_4 = 2, 912 BRW_WIDTH_8 = 3, 913 BRW_WIDTH_16 = 4, 914 }; 915 916 /** 917 * Message target: Shared Function ID for where to SEND a message. 918 * 919 * These are enumerated in the ISA reference under "send - Send Message". 920 * In particular, see the following tables: 921 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition" 922 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor" 923 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs" 924 */ 925 enum brw_message_target { 926 BRW_SFID_NULL = 0, 927 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */ 928 BRW_SFID_SAMPLER = 2, 929 BRW_SFID_MESSAGE_GATEWAY = 3, 930 BRW_SFID_DATAPORT_READ = 4, 931 BRW_SFID_DATAPORT_WRITE = 5, 932 BRW_SFID_URB = 6, 933 BRW_SFID_THREAD_SPAWNER = 7, 934 BRW_SFID_VME = 8, 935 936 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4, 937 GEN6_SFID_DATAPORT_RENDER_CACHE = 5, 938 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9, 939 940 GEN7_SFID_DATAPORT_DATA_CACHE = 10, 941 GEN7_SFID_PIXEL_INTERPOLATOR = 11, 942 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12, 943 HSW_SFID_CRE = 13, 944 }; 945 946 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10 947 948 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 949 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 950 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 951 952 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 953 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 954 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 955 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 956 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 957 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 958 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 959 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 960 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 961 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 962 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 963 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 964 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 965 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 966 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 967 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 968 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 969 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 970 971 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0 972 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 973 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2 974 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3 975 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4 976 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5 977 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6 978 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7 979 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8 980 #define GEN5_SAMPLER_MESSAGE_LOD 9 981 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10 982 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11 983 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16 984 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17 985 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18 986 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20 987 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24 988 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25 989 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26 990 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28 991 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29 992 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30 993 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31 994 995 /* for GEN5 only */ 996 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 997 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1 998 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2 999 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3 1000 1001 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2 1002 * behavior by setting bit 22 of dword 2 in the message header. */ 1003 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0 1004 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22) 1005 1006 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 1007 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 1008 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 1009 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 1010 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 1011 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \ 1012 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ 1013 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \ 1014 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \ 1015 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \ 1016 (abort(), ~0)) 1017 1018 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 1019 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 1020 1021 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 1022 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 1023 1024 /* This one stays the same across generations. */ 1025 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 1026 /* GEN4 */ 1027 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 1028 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 1029 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 1030 /* G45, GEN5 */ 1031 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 1032 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 1033 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3 1034 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 1035 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 1036 /* GEN6 */ 1037 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 1038 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 1039 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 1040 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 1041 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 1042 1043 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 1044 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 1045 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 1046 1047 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 1048 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 1049 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 1050 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 1051 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 1052 1053 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 1054 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 1055 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 1056 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 1057 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 1058 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 1059 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 1060 1061 /* GEN6 */ 1062 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 1063 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 1064 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 1065 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 1066 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11 1067 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 1068 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 1069 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 1070 1071 /* GEN7 */ 1072 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4 1073 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5 1074 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6 1075 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7 1076 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10 1077 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12 1078 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13 1079 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0 1080 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1 1081 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2 1082 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3 1083 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4 1084 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5 1085 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6 1086 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7 1087 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8 1088 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10 1089 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11 1090 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12 1091 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13 1092 1093 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \ 1094 (0 << 17)) 1095 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \ 1096 (1 << 17)) 1097 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12 1098 1099 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0 1100 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1 1101 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2 1102 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3 1103 1104 /* HSW */ 1105 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0 1106 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1 1107 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2 1108 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3 1109 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4 1110 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7 1111 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8 1112 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10 1113 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11 1114 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12 1115 1116 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1 1117 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2 1118 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3 1119 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4 1120 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5 1121 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6 1122 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7 1123 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9 1124 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10 1125 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11 1126 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12 1127 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13 1128 1129 /* GEN9 */ 1130 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12 1131 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13 1132 1133 /* Dataport special binding table indices: */ 1134 #define BRW_BTI_STATELESS 255 1135 #define GEN7_BTI_SLM 254 1136 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the 1137 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, 1138 * CHV and at least some pre-production steppings of SKL due to 1139 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the 1140 * kernel to be non-coherent (matching the behavior of the same BTI on 1141 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253. 1142 */ 1143 #define GEN8_BTI_STATELESS_IA_COHERENT 255 1144 #define GEN8_BTI_STATELESS_NON_COHERENT 253 1145 1146 /* dataport atomic operations. */ 1147 #define BRW_AOP_AND 1 1148 #define BRW_AOP_OR 2 1149 #define BRW_AOP_XOR 3 1150 #define BRW_AOP_MOV 4 1151 #define BRW_AOP_INC 5 1152 #define BRW_AOP_DEC 6 1153 #define BRW_AOP_ADD 7 1154 #define BRW_AOP_SUB 8 1155 #define BRW_AOP_REVSUB 9 1156 #define BRW_AOP_IMAX 10 1157 #define BRW_AOP_IMIN 11 1158 #define BRW_AOP_UMAX 12 1159 #define BRW_AOP_UMIN 13 1160 #define BRW_AOP_CMPWR 14 1161 #define BRW_AOP_PREDEC 15 1162 1163 #define BRW_MATH_FUNCTION_INV 1 1164 #define BRW_MATH_FUNCTION_LOG 2 1165 #define BRW_MATH_FUNCTION_EXP 3 1166 #define BRW_MATH_FUNCTION_SQRT 4 1167 #define BRW_MATH_FUNCTION_RSQ 5 1168 #define BRW_MATH_FUNCTION_SIN 6 1169 #define BRW_MATH_FUNCTION_COS 7 1170 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */ 1171 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */ 1172 #define BRW_MATH_FUNCTION_POW 10 1173 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 1174 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 1175 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 1176 #define GEN8_MATH_FUNCTION_INVM 14 1177 #define GEN8_MATH_FUNCTION_RSQRTM 15 1178 1179 #define BRW_MATH_INTEGER_UNSIGNED 0 1180 #define BRW_MATH_INTEGER_SIGNED 1 1181 1182 #define BRW_MATH_PRECISION_FULL 0 1183 #define BRW_MATH_PRECISION_PARTIAL 1 1184 1185 #define BRW_MATH_SATURATE_NONE 0 1186 #define BRW_MATH_SATURATE_SATURATE 1 1187 1188 #define BRW_MATH_DATA_VECTOR 0 1189 #define BRW_MATH_DATA_SCALAR 1 1190 1191 #define BRW_URB_OPCODE_WRITE_HWORD 0 1192 #define BRW_URB_OPCODE_WRITE_OWORD 1 1193 #define BRW_URB_OPCODE_READ_HWORD 2 1194 #define BRW_URB_OPCODE_READ_OWORD 3 1195 #define GEN7_URB_OPCODE_ATOMIC_MOV 4 1196 #define GEN7_URB_OPCODE_ATOMIC_INC 5 1197 #define GEN8_URB_OPCODE_ATOMIC_ADD 6 1198 #define GEN8_URB_OPCODE_SIMD8_WRITE 7 1199 #define GEN8_URB_OPCODE_SIMD8_READ 8 1200 1201 #define BRW_URB_SWIZZLE_NONE 0 1202 #define BRW_URB_SWIZZLE_INTERLEAVE 1 1203 #define BRW_URB_SWIZZLE_TRANSPOSE 2 1204 1205 #define BRW_SCRATCH_SPACE_SIZE_1K 0 1206 #define BRW_SCRATCH_SPACE_SIZE_2K 1 1207 #define BRW_SCRATCH_SPACE_SIZE_4K 2 1208 #define BRW_SCRATCH_SPACE_SIZE_8K 3 1209 #define BRW_SCRATCH_SPACE_SIZE_16K 4 1210 #define BRW_SCRATCH_SPACE_SIZE_32K 5 1211 #define BRW_SCRATCH_SPACE_SIZE_64K 6 1212 #define BRW_SCRATCH_SPACE_SIZE_128K 7 1213 #define BRW_SCRATCH_SPACE_SIZE_256K 8 1214 #define BRW_SCRATCH_SPACE_SIZE_512K 9 1215 #define BRW_SCRATCH_SPACE_SIZE_1M 10 1216 #define BRW_SCRATCH_SPACE_SIZE_2M 11 1217 1218 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0 1219 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1 1220 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2 1221 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3 1222 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4 1223 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5 1224 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6 1225 1226 1227 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size 1228 * is 2^9, or 512. It's counted in multiples of 64 bytes. 1229 * 1230 * Identical for VS, DS, and HS. 1231 */ 1232 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64) 1233 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64) 1234 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64) 1235 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64) 1236 1237 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit 1238 * (128 bytes) URB rows and the maximum allowed value is 5 rows. 1239 */ 1240 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128) 1241 1242 /* GS Thread Payload 1243 */ 1244 1245 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's 1246 * counted in multiples of 16 bytes. 1247 */ 1248 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16) 1249 1250 1251 /* R0 */ 1252 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27 1253 1254 /* CR0.0[5:4] Floating-Point Rounding Modes 1255 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756 1256 */ 1257 1258 #define BRW_CR0_RND_MODE_MASK 0x30 1259 #define BRW_CR0_RND_MODE_SHIFT 4 1260 1261 enum PACKED brw_rnd_mode { 1262 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */ 1263 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */ 1264 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */ 1265 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */ 1266 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */ 1267 }; 1268 1269 /* MDC_DS - Data Size Message Descriptor Control Field 1270 * Skylake PRM, Volume 2d, page 129 1271 * 1272 * Specifies the number of Bytes to be read or written per Dword used at 1273 * byte_scattered read/write and byte_scaled read/write messages. 1274 */ 1275 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0 1276 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1 1277 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2 1278 1279 #endif /* BRW_EU_DEFINES_H */ 1280
