1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_ENGINE_H_ 7 #define _DDR3_TRAINING_IP_ENGINE_H_ 8 9 #include "ddr3_training_ip_def.h" 10 #include "ddr3_training_ip_flow.h" 11 12 #define EDGE_1 0 13 #define EDGE_2 1 14 #define ALL_PUP_TRAINING 0xe 15 #define PUP_RESULT_EDGE_1_MASK 0xff 16 #define PUP_RESULT_EDGE_2_MASK (0xff << 8) 17 #define PUP_LOCK_RESULT_BIT 25 18 19 #define GET_TAP_RESULT(reg, edge) \ 20 (((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \ 21 (((reg) & PUP_RESULT_EDGE_2_MASK) >> 8)); 22 #define GET_LOCK_RESULT(reg) \ 23 (((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT) 24 25 #define EDGE_FAILURE 128 26 #define ALL_BITS_PER_PUP 128 27 28 #define MIN_WINDOW_SIZE 6 29 #define MAX_WINDOW_SIZE_RX 32 30 #define MAX_WINDOW_SIZE_TX 64 31 32 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type, 33 enum hws_search_dir search_dir, 34 enum hws_dir direction, 35 enum hws_edge_compare edge, 36 u32 init_val1, u32 init_val2, 37 u32 num_of_iterations, u32 start_pattern, 38 u32 end_pattern); 39 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern); 40 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num); 41 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, 42 enum hws_access_type pup_access_type, 43 u32 pup_num, u32 bit_num, 44 enum hws_search_dir search, 45 enum hws_dir direction, 46 enum hws_training_result result_type, 47 enum hws_training_load_op operation, 48 u32 cs_num_type, u32 **load_res, 49 int is_read_from_db, u8 cons_tap, 50 int is_check_result_validity); 51 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, 52 u32 interface_num, 53 enum hws_access_type pup_access_type, 54 u32 pup_num, enum hws_training_result result_type, 55 enum hws_control_element control_element, 56 enum hws_search_dir search_dir, enum hws_dir direction, 57 u32 interface_mask, u32 init_value, u32 num_iter, 58 enum hws_pattern pattern, 59 enum hws_edge_compare edge_comp, 60 enum hws_ddr_cs cs_type, u32 cs_num, 61 enum hws_training_ip_stat *train_status); 62 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, 63 u32 if_id, 64 enum hws_access_type pup_access_type, 65 u32 pup_num, 66 enum hws_training_result result_type, 67 enum hws_control_element control_element, 68 enum hws_search_dir search_dir, 69 enum hws_dir direction, 70 u32 interface_mask, u32 init_value1, 71 u32 init_value2, u32 num_iter, 72 enum hws_pattern pattern, 73 enum hws_edge_compare edge_comp, 74 enum hws_ddr_cs train_cs_type, u32 cs_num, 75 enum hws_training_ip_stat *train_status); 76 u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id); 77 void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data); 78 void ddr3_tip_print_bist_res(void); 79 struct pattern_info *ddr3_tip_get_pattern_table(void); 80 u16 *ddr3_tip_get_mask_results_dq_reg(void); 81 u16 *ddr3_tip_get_mask_results_pup_reg_map(void); 82 int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern, 83 enum dm_direction dm_dir); 84 int mv_ddr_pattern_start_addr_set(struct pattern_info *pattern_tbl, enum hws_pattern pattern, u32 addr); 85 #endif /* _DDR3_TRAINING_IP_ENGINE_H_ */ 86
