1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the X86 target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 19 20 #include "X86MCTargetDesc.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/Support/DataTypes.h" 23 #include "llvm/Support/ErrorHandling.h" 24 25 namespace llvm { 26 27 namespace X86 { 28 // Enums for memory operand decoding. Each memory operand is represented with 29 // a 5 operand sequence in the form: 30 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 31 // These enums help decode this. 32 enum { 33 AddrBaseReg = 0, 34 AddrScaleAmt = 1, 35 AddrIndexReg = 2, 36 AddrDisp = 3, 37 38 /// AddrSegmentReg - The operand # of the segment in the memory operand. 39 AddrSegmentReg = 4, 40 41 /// AddrNumOperands - Total number of operands in a memory reference. 42 AddrNumOperands = 5 43 }; 44 45 /// AVX512 static rounding constants. These need to match the values in 46 /// avx512fintrin.h. 47 enum STATIC_ROUNDING { 48 TO_NEAREST_INT = 0, 49 TO_NEG_INF = 1, 50 TO_POS_INF = 2, 51 TO_ZERO = 3, 52 CUR_DIRECTION = 4 53 }; 54 55 /// The constants to describe instr prefixes if there are 56 enum IPREFIXES { 57 IP_NO_PREFIX = 0, 58 IP_HAS_OP_SIZE = 1, 59 IP_HAS_AD_SIZE = 2, 60 IP_HAS_REPEAT_NE = 4, 61 IP_HAS_REPEAT = 8, 62 IP_HAS_LOCK = 16, 63 NO_SCHED_INFO = 32, // Don't add sched comment to the current instr because 64 // it was already added 65 IP_HAS_NOTRACK = 64 66 }; 67 } // end namespace X86; 68 69 /// X86II - This namespace holds all of the target specific flags that 70 /// instruction info tracks. 71 /// 72 namespace X86II { 73 /// Target Operand Flag enum. 74 enum TOF { 75 //===------------------------------------------------------------------===// 76 // X86 Specific MachineOperand flags. 77 78 MO_NO_FLAG, 79 80 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 81 /// relocation of: 82 /// SYMBOL_LABEL + [. - PICBASELABEL] 83 MO_GOT_ABSOLUTE_ADDRESS, 84 85 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 86 /// immediate should get the value of the symbol minus the PIC base label: 87 /// SYMBOL_LABEL - PICBASELABEL 88 MO_PIC_BASE_OFFSET, 89 90 /// MO_GOT - On a symbol operand this indicates that the immediate is the 91 /// offset to the GOT entry for the symbol name from the base of the GOT. 92 /// 93 /// See the X86-64 ELF ABI supplement for more details. 94 /// SYMBOL_LABEL @GOT 95 MO_GOT, 96 97 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 98 /// the offset to the location of the symbol name from the base of the GOT. 99 /// 100 /// See the X86-64 ELF ABI supplement for more details. 101 /// SYMBOL_LABEL @GOTOFF 102 MO_GOTOFF, 103 104 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 105 /// offset to the GOT entry for the symbol name from the current code 106 /// location. 107 /// 108 /// See the X86-64 ELF ABI supplement for more details. 109 /// SYMBOL_LABEL @GOTPCREL 110 MO_GOTPCREL, 111 112 /// MO_PLT - On a symbol operand this indicates that the immediate is 113 /// offset to the PLT entry of symbol name from the current code location. 114 /// 115 /// See the X86-64 ELF ABI supplement for more details. 116 /// SYMBOL_LABEL @PLT 117 MO_PLT, 118 119 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 120 /// the offset of the GOT entry with the TLS index structure that contains 121 /// the module number and variable offset for the symbol. Used in the 122 /// general dynamic TLS access model. 123 /// 124 /// See 'ELF Handling for Thread-Local Storage' for more details. 125 /// SYMBOL_LABEL @TLSGD 126 MO_TLSGD, 127 128 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 129 /// the offset of the GOT entry with the TLS index for the module that 130 /// contains the symbol. When this index is passed to a call to 131 /// __tls_get_addr, the function will return the base address of the TLS 132 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 133 /// 134 /// See 'ELF Handling for Thread-Local Storage' for more details. 135 /// SYMBOL_LABEL @TLSLD 136 MO_TLSLD, 137 138 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 139 /// the offset of the GOT entry with the TLS index for the module that 140 /// contains the symbol. When this index is passed to a call to 141 /// ___tls_get_addr, the function will return the base address of the TLS 142 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 143 /// 144 /// See 'ELF Handling for Thread-Local Storage' for more details. 145 /// SYMBOL_LABEL @TLSLDM 146 MO_TLSLDM, 147 148 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 149 /// the offset of the GOT entry with the thread-pointer offset for the 150 /// symbol. Used in the x86-64 initial exec TLS access model. 151 /// 152 /// See 'ELF Handling for Thread-Local Storage' for more details. 153 /// SYMBOL_LABEL @GOTTPOFF 154 MO_GOTTPOFF, 155 156 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 157 /// the absolute address of the GOT entry with the negative thread-pointer 158 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 159 /// model. 160 /// 161 /// See 'ELF Handling for Thread-Local Storage' for more details. 162 /// SYMBOL_LABEL @INDNTPOFF 163 MO_INDNTPOFF, 164 165 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 166 /// the thread-pointer offset for the symbol. Used in the x86-64 local 167 /// exec TLS access model. 168 /// 169 /// See 'ELF Handling for Thread-Local Storage' for more details. 170 /// SYMBOL_LABEL @TPOFF 171 MO_TPOFF, 172 173 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 174 /// the offset of the GOT entry with the TLS offset of the symbol. Used 175 /// in the local dynamic TLS access model. 176 /// 177 /// See 'ELF Handling for Thread-Local Storage' for more details. 178 /// SYMBOL_LABEL @DTPOFF 179 MO_DTPOFF, 180 181 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 182 /// the negative thread-pointer offset for the symbol. Used in the IA32 183 /// local exec TLS access model. 184 /// 185 /// See 'ELF Handling for Thread-Local Storage' for more details. 186 /// SYMBOL_LABEL @NTPOFF 187 MO_NTPOFF, 188 189 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 190 /// the offset of the GOT entry with the negative thread-pointer offset for 191 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 192 /// 193 /// See 'ELF Handling for Thread-Local Storage' for more details. 194 /// SYMBOL_LABEL @GOTNTPOFF 195 MO_GOTNTPOFF, 196 197 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 198 /// reference is actually to the "__imp_FOO" symbol. This is used for 199 /// dllimport linkage on windows. 200 MO_DLLIMPORT, 201 202 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 203 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 204 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 205 MO_DARWIN_NONLAZY, 206 207 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 208 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 209 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 210 MO_DARWIN_NONLAZY_PIC_BASE, 211 212 /// MO_TLVP - On a symbol operand this indicates that the immediate is 213 /// some TLS offset. 214 /// 215 /// This is the TLS offset for the Darwin TLS mechanism. 216 MO_TLVP, 217 218 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 219 /// is some TLS offset from the picbase. 220 /// 221 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 222 MO_TLVP_PIC_BASE, 223 224 /// MO_SECREL - On a symbol operand this indicates that the immediate is 225 /// the offset from beginning of section. 226 /// 227 /// This is the TLS offset for the COFF/Windows TLS mechanism. 228 MO_SECREL, 229 230 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known 231 /// to be an absolute symbol in range [0,128), so we can use the @ABS8 232 /// symbol modifier. 233 MO_ABS8, 234 }; 235 236 enum : uint64_t { 237 //===------------------------------------------------------------------===// 238 // Instruction encodings. These are the standard/most common forms for X86 239 // instructions. 240 // 241 242 // PseudoFrm - This represents an instruction that is a pseudo instruction 243 // or one that has not been implemented yet. It is illegal to code generate 244 // it, but tolerated for intermediate implementation stages. 245 Pseudo = 0, 246 247 /// Raw - This form is for instructions that don't have any operands, so 248 /// they are just a fixed opcode value, like 'leave'. 249 RawFrm = 1, 250 251 /// AddRegFrm - This form is used for instructions like 'push r32' that have 252 /// their one register operand added to their opcode. 253 AddRegFrm = 2, 254 255 /// RawFrmMemOffs - This form is for instructions that store an absolute 256 /// memory offset as an immediate with a possible segment override. 257 RawFrmMemOffs = 3, 258 259 /// RawFrmSrc - This form is for instructions that use the source index 260 /// register SI/ESI/RSI with a possible segment override. 261 RawFrmSrc = 4, 262 263 /// RawFrmDst - This form is for instructions that use the destination index 264 /// register DI/EDI/ESI. 265 RawFrmDst = 5, 266 267 /// RawFrmSrc - This form is for instructions that use the source index 268 /// register SI/ESI/ERI with a possible segment override, and also the 269 /// destination index register DI/ESI/RDI. 270 RawFrmDstSrc = 6, 271 272 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 273 /// immediates, the first of which is a 16-bit immediate (specified by 274 /// the imm encoding) and the second is a 8-bit fixed value. 275 RawFrmImm8 = 7, 276 277 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 278 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 279 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 280 /// manual, this operand is described as pntr16:32 and pntr16:16 281 RawFrmImm16 = 8, 282 283 /// MRM[0-7][rm] - These forms are used to represent instructions that use 284 /// a Mod/RM byte, and use the middle field to hold extended opcode 285 /// information. In the intel manual these are represented as /0, /1, ... 286 /// 287 288 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 289 /// to specify a destination, which in this case is memory. 290 /// 291 MRMDestMem = 32, 292 293 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 294 /// to specify a source, which in this case is memory. 295 /// 296 MRMSrcMem = 33, 297 298 /// MRMSrcMem4VOp3 - This form is used for instructions that encode 299 /// operand 3 with VEX.VVVV and load from memory. 300 /// 301 MRMSrcMem4VOp3 = 34, 302 303 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM 304 /// byte to specify the fourth source, which in this case is memory. 305 /// 306 MRMSrcMemOp4 = 35, 307 308 /// MRMXm - This form is used for instructions that use the Mod/RM byte 309 /// to specify a memory source, but doesn't use the middle field. 310 /// 311 MRMXm = 39, // Instruction that uses Mod/RM but not the middle field. 312 313 // Next, instructions that operate on a memory r/m operand... 314 MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3 315 MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7 316 317 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 318 /// to specify a destination, which in this case is a register. 319 /// 320 MRMDestReg = 48, 321 322 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 323 /// to specify a source, which in this case is a register. 324 /// 325 MRMSrcReg = 49, 326 327 /// MRMSrcReg4VOp3 - This form is used for instructions that encode 328 /// operand 3 with VEX.VVVV and do not load from memory. 329 /// 330 MRMSrcReg4VOp3 = 50, 331 332 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM 333 /// byte to specify the fourth source, which in this case is a register. 334 /// 335 MRMSrcRegOp4 = 51, 336 337 /// MRMXr - This form is used for instructions that use the Mod/RM byte 338 /// to specify a register source, but doesn't use the middle field. 339 /// 340 MRMXr = 55, // Instruction that uses Mod/RM but not the middle field. 341 342 // Instructions that operate on a register r/m operand... 343 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 344 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 345 346 /// MRM_XX - A mod/rm byte of exactly 0xXX. 347 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, 348 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, 349 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, 350 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, 351 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, 352 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, 353 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, 354 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, 355 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, 356 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, 357 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, 358 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, 359 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, 360 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, 361 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, 362 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, 363 364 FormMask = 127, 365 366 //===------------------------------------------------------------------===// 367 // Actual flags... 368 369 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 370 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 371 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 372 // prefix in 16-bit mode. 373 OpSizeShift = 7, 374 OpSizeMask = 0x3 << OpSizeShift, 375 376 OpSizeFixed = 0 << OpSizeShift, 377 OpSize16 = 1 << OpSizeShift, 378 OpSize32 = 2 << OpSizeShift, 379 380 // AsSize - AdSizeX implies this instruction determines its need of 0x67 381 // prefix from a normal ModRM memory operand. The other types indicate that 382 // an operand is encoded with a specific width and a prefix is needed if 383 // it differs from the current mode. 384 AdSizeShift = OpSizeShift + 2, 385 AdSizeMask = 0x3 << AdSizeShift, 386 387 AdSizeX = 0 << AdSizeShift, 388 AdSize16 = 1 << AdSizeShift, 389 AdSize32 = 2 << AdSizeShift, 390 AdSize64 = 3 << AdSizeShift, 391 392 //===------------------------------------------------------------------===// 393 // OpPrefix - There are several prefix bytes that are used as opcode 394 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 395 // no prefix. 396 // 397 OpPrefixShift = AdSizeShift + 2, 398 OpPrefixMask = 0x3 << OpPrefixShift, 399 400 // PD - Prefix code for packed double precision vector floating point 401 // operations performed in the SSE registers. 402 PD = 1 << OpPrefixShift, 403 404 // XS, XD - These prefix codes are for single and double precision scalar 405 // floating point operations performed in the SSE registers. 406 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift, 407 408 //===------------------------------------------------------------------===// 409 // OpMap - This field determines which opcode map this instruction 410 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 411 // 412 OpMapShift = OpPrefixShift + 2, 413 OpMapMask = 0x7 << OpMapShift, 414 415 // OB - OneByte - Set if this instruction has a one byte opcode. 416 OB = 0 << OpMapShift, 417 418 // TB - TwoByte - Set if this instruction has a two byte opcode, which 419 // starts with a 0x0F byte before the real opcode. 420 TB = 1 << OpMapShift, 421 422 // T8, TA - Prefix after the 0x0F prefix. 423 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 424 425 // XOP8 - Prefix to include use of imm byte. 426 XOP8 = 4 << OpMapShift, 427 428 // XOP9 - Prefix to exclude use of imm byte. 429 XOP9 = 5 << OpMapShift, 430 431 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 432 XOPA = 6 << OpMapShift, 433 434 /// ThreeDNow - This indicates that the instruction uses the 435 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 436 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 437 /// storing a classifier in the imm8 field. To simplify our implementation, 438 /// we handle this by storeing the classifier in the opcode field and using 439 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 440 ThreeDNow = 7 << OpMapShift, 441 442 //===------------------------------------------------------------------===// 443 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 444 // They are used to specify GPRs and SSE registers, 64-bit operand size, 445 // etc. We only cares about REX.W and REX.R bits and only the former is 446 // statically determined. 447 // 448 REXShift = OpMapShift + 3, 449 REX_W = 1 << REXShift, 450 451 //===------------------------------------------------------------------===// 452 // This three-bit field describes the size of an immediate operand. Zero is 453 // unused so that we can tell if we forgot to set a value. 454 ImmShift = REXShift + 1, 455 ImmMask = 15 << ImmShift, 456 Imm8 = 1 << ImmShift, 457 Imm8PCRel = 2 << ImmShift, 458 Imm8Reg = 3 << ImmShift, 459 Imm16 = 4 << ImmShift, 460 Imm16PCRel = 5 << ImmShift, 461 Imm32 = 6 << ImmShift, 462 Imm32PCRel = 7 << ImmShift, 463 Imm32S = 8 << ImmShift, 464 Imm64 = 9 << ImmShift, 465 466 //===------------------------------------------------------------------===// 467 // FP Instruction Classification... Zero is non-fp instruction. 468 469 // FPTypeMask - Mask for all of the FP types... 470 FPTypeShift = ImmShift + 4, 471 FPTypeMask = 7 << FPTypeShift, 472 473 // NotFP - The default, set for instructions that do not use FP registers. 474 NotFP = 0 << FPTypeShift, 475 476 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 477 ZeroArgFP = 1 << FPTypeShift, 478 479 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 480 OneArgFP = 2 << FPTypeShift, 481 482 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 483 // result back to ST(0). For example, fcos, fsqrt, etc. 484 // 485 OneArgFPRW = 3 << FPTypeShift, 486 487 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 488 // explicit argument, storing the result to either ST(0) or the implicit 489 // argument. For example: fadd, fsub, fmul, etc... 490 TwoArgFP = 4 << FPTypeShift, 491 492 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 493 // explicit argument, but have no destination. Example: fucom, fucomi, ... 494 CompareFP = 5 << FPTypeShift, 495 496 // CondMovFP - "2 operand" floating point conditional move instructions. 497 CondMovFP = 6 << FPTypeShift, 498 499 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 500 SpecialFP = 7 << FPTypeShift, 501 502 // Lock prefix 503 LOCKShift = FPTypeShift + 3, 504 LOCK = 1 << LOCKShift, 505 506 // REP prefix 507 REPShift = LOCKShift + 1, 508 REP = 1 << REPShift, 509 510 // Execution domain for SSE instructions. 511 // 0 means normal, non-SSE instruction. 512 SSEDomainShift = REPShift + 1, 513 514 // Encoding 515 EncodingShift = SSEDomainShift + 2, 516 EncodingMask = 0x3 << EncodingShift, 517 518 // VEX - encoding using 0xC4/0xC5 519 VEX = 1 << EncodingShift, 520 521 /// XOP - Opcode prefix used by XOP instructions. 522 XOP = 2 << EncodingShift, 523 524 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 525 // syntax support up to 32 512-bit register operands and up to 7 16-bit 526 // mask operands as well as source operand data swizzling/memory operand 527 // conversion, eviction hint, and rounding mode. 528 EVEX = 3 << EncodingShift, 529 530 // Opcode 531 OpcodeShift = EncodingShift + 2, 532 533 /// VEX_W - Has a opcode specific functionality, but is used in the same 534 /// way as REX_W is for regular SSE instructions. 535 VEX_WShift = OpcodeShift + 8, 536 VEX_W = 1ULL << VEX_WShift, 537 538 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 539 /// address instructions in SSE are represented as 3 address ones in AVX 540 /// and the additional register is encoded in VEX_VVVV prefix. 541 VEX_4VShift = VEX_WShift + 1, 542 VEX_4V = 1ULL << VEX_4VShift, 543 544 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 545 /// instruction uses 256-bit wide registers. This is usually auto detected 546 /// if a VR256 register is used, but some AVX instructions also have this 547 /// field marked when using a f256 memory references. 548 VEX_LShift = VEX_4VShift + 1, 549 VEX_L = 1ULL << VEX_LShift, 550 551 // EVEX_K - Set if this instruction requires masking 552 EVEX_KShift = VEX_LShift + 1, 553 EVEX_K = 1ULL << EVEX_KShift, 554 555 // EVEX_Z - Set if this instruction has EVEX.Z field set. 556 EVEX_ZShift = EVEX_KShift + 1, 557 EVEX_Z = 1ULL << EVEX_ZShift, 558 559 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 560 EVEX_L2Shift = EVEX_ZShift + 1, 561 EVEX_L2 = 1ULL << EVEX_L2Shift, 562 563 // EVEX_B - Set if this instruction has EVEX.B field set. 564 EVEX_BShift = EVEX_L2Shift + 1, 565 EVEX_B = 1ULL << EVEX_BShift, 566 567 // The scaling factor for the AVX512's 8-bit compressed displacement. 568 CD8_Scale_Shift = EVEX_BShift + 1, 569 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 570 571 /// Explicitly specified rounding control 572 EVEX_RCShift = CD8_Scale_Shift + 7, 573 EVEX_RC = 1ULL << EVEX_RCShift, 574 575 // NOTRACK prefix 576 NoTrackShift = EVEX_RCShift + 1, 577 NOTRACK = 1ULL << NoTrackShift 578 }; 579 580 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 581 // specified machine instruction. 582 // 583 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { 584 return TSFlags >> X86II::OpcodeShift; 585 } 586 587 inline bool hasImm(uint64_t TSFlags) { 588 return (TSFlags & X86II::ImmMask) != 0; 589 } 590 591 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 592 /// of the specified instruction. 593 inline unsigned getSizeOfImm(uint64_t TSFlags) { 594 switch (TSFlags & X86II::ImmMask) { 595 default: llvm_unreachable("Unknown immediate size"); 596 case X86II::Imm8: 597 case X86II::Imm8PCRel: 598 case X86II::Imm8Reg: return 1; 599 case X86II::Imm16: 600 case X86II::Imm16PCRel: return 2; 601 case X86II::Imm32: 602 case X86II::Imm32S: 603 case X86II::Imm32PCRel: return 4; 604 case X86II::Imm64: return 8; 605 } 606 } 607 608 /// isImmPCRel - Return true if the immediate of the specified instruction's 609 /// TSFlags indicates that it is pc relative. 610 inline unsigned isImmPCRel(uint64_t TSFlags) { 611 switch (TSFlags & X86II::ImmMask) { 612 default: llvm_unreachable("Unknown immediate size"); 613 case X86II::Imm8PCRel: 614 case X86II::Imm16PCRel: 615 case X86II::Imm32PCRel: 616 return true; 617 case X86II::Imm8: 618 case X86II::Imm8Reg: 619 case X86II::Imm16: 620 case X86II::Imm32: 621 case X86II::Imm32S: 622 case X86II::Imm64: 623 return false; 624 } 625 } 626 627 /// isImmSigned - Return true if the immediate of the specified instruction's 628 /// TSFlags indicates that it is signed. 629 inline unsigned isImmSigned(uint64_t TSFlags) { 630 switch (TSFlags & X86II::ImmMask) { 631 default: llvm_unreachable("Unknown immediate signedness"); 632 case X86II::Imm32S: 633 return true; 634 case X86II::Imm8: 635 case X86II::Imm8PCRel: 636 case X86II::Imm8Reg: 637 case X86II::Imm16: 638 case X86II::Imm16PCRel: 639 case X86II::Imm32: 640 case X86II::Imm32PCRel: 641 case X86II::Imm64: 642 return false; 643 } 644 } 645 646 /// getOperandBias - compute whether all of the def operands are repeated 647 /// in the uses and therefore should be skipped. 648 /// This determines the start of the unique operand list. We need to determine 649 /// if all of the defs have a corresponding tied operand in the uses. 650 /// Unfortunately, the tied operand information is encoded in the uses not 651 /// the defs so we have to use some heuristics to find which operands to 652 /// query. 653 inline unsigned getOperandBias(const MCInstrDesc& Desc) { 654 unsigned NumDefs = Desc.getNumDefs(); 655 unsigned NumOps = Desc.getNumOperands(); 656 switch (NumDefs) { 657 default: llvm_unreachable("Unexpected number of defs"); 658 case 0: 659 return 0; 660 case 1: 661 // Common two addr case. 662 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 663 return 1; 664 // Check for AVX-512 scatter which has a TIED_TO in the second to last 665 // operand. 666 if (NumOps == 8 && 667 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) 668 return 1; 669 return 0; 670 case 2: 671 // XCHG/XADD have two destinations and two sources. 672 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 673 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 674 return 2; 675 // Check for gather. AVX-512 has the second tied operand early. AVX2 676 // has it as the last op. 677 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 678 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || 679 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1) && 680 "Instruction with 2 defs isn't gather?") 681 return 2; 682 return 0; 683 } 684 } 685 686 /// getMemoryOperandNo - The function returns the MCInst operand # for the 687 /// first field of the memory operand. If the instruction doesn't have a 688 /// memory operand, this returns -1. 689 /// 690 /// Note that this ignores tied operands. If there is a tied register which 691 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 692 /// counted as one operand. 693 /// 694 inline int getMemoryOperandNo(uint64_t TSFlags) { 695 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 696 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 697 698 switch (TSFlags & X86II::FormMask) { 699 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 700 case X86II::Pseudo: 701 case X86II::RawFrm: 702 case X86II::AddRegFrm: 703 case X86II::RawFrmImm8: 704 case X86II::RawFrmImm16: 705 case X86II::RawFrmMemOffs: 706 case X86II::RawFrmSrc: 707 case X86II::RawFrmDst: 708 case X86II::RawFrmDstSrc: 709 return -1; 710 case X86II::MRMDestMem: 711 return 0; 712 case X86II::MRMSrcMem: 713 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 714 // mask register. 715 return 1 + HasVEX_4V + HasEVEX_K; 716 case X86II::MRMSrcMem4VOp3: 717 // Skip registers encoded in reg. 718 return 1 + HasEVEX_K; 719 case X86II::MRMSrcMemOp4: 720 // Skip registers encoded in reg, VEX_VVVV, and I8IMM. 721 return 3; 722 case X86II::MRMDestReg: 723 case X86II::MRMSrcReg: 724 case X86II::MRMSrcReg4VOp3: 725 case X86II::MRMSrcRegOp4: 726 case X86II::MRMXr: 727 case X86II::MRM0r: case X86II::MRM1r: 728 case X86II::MRM2r: case X86II::MRM3r: 729 case X86II::MRM4r: case X86II::MRM5r: 730 case X86II::MRM6r: case X86II::MRM7r: 731 return -1; 732 case X86II::MRMXm: 733 case X86II::MRM0m: case X86II::MRM1m: 734 case X86II::MRM2m: case X86II::MRM3m: 735 case X86II::MRM4m: case X86II::MRM5m: 736 case X86II::MRM6m: case X86II::MRM7m: 737 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 738 return 0 + HasVEX_4V + HasEVEX_K; 739 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 740 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 741 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 742 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 743 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 744 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 745 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 746 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 747 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 748 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 749 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 750 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 751 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 752 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 753 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 754 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 755 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 756 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 757 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 758 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 759 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 760 case X86II::MRM_FF: 761 return -1; 762 } 763 } 764 765 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 766 /// higher) register? e.g. r8, xmm8, xmm13, etc. 767 inline bool isX86_64ExtendedReg(unsigned RegNo) { 768 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || 769 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) || 770 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31)) 771 return true; 772 773 switch (RegNo) { 774 default: break; 775 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 776 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 777 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 778 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 779 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 780 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 781 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 782 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 783 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 784 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 785 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11: 786 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15: 787 return true; 788 } 789 return false; 790 } 791 792 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) 793 /// registers? e.g. zmm21, etc. 794 static inline bool is32ExtendedReg(unsigned RegNo) { 795 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || 796 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) || 797 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31)); 798 } 799 800 801 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 802 return (reg == X86::SPL || reg == X86::BPL || 803 reg == X86::SIL || reg == X86::DIL); 804 } 805 806 /// isKMasked - Is this a masked instruction. 807 inline bool isKMasked(uint64_t TSFlags) { 808 return (TSFlags & X86II::EVEX_K) != 0; 809 } 810 811 /// isKMergedMasked - Is this a merge masked instruction. 812 inline bool isKMergeMasked(uint64_t TSFlags) { 813 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0; 814 } 815 } 816 817 } // end namespace llvm; 818 819 #endif 820
