1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /*------------------------------------------------------------------------ 3 * lan91c96.h 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Rolf Offermanns <rof (at) sysgo.de> 8 * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 9 * Developed by Simple Network Magic Corporation (SNMC) 10 * Copyright (C) 1996 by Erik Stahlman (ES) 11 * 12 * This file contains register information and access macros for 13 * the LAN91C96 single chip ethernet controller. It is a modified 14 * version of the smc9111.h file. 15 * 16 * Information contained in this file was obtained from the LAN91C96 17 * manual from SMC. To get a copy, if you really want one, you can find 18 * information under www.smsc.com. 19 * 20 * Authors 21 * Erik Stahlman ( erik (at) vt.edu ) 22 * Daris A Nevil ( dnevil (at) snmc.com ) 23 * 24 * History 25 * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) 26 * for lan91c96 27 *------------------------------------------------------------------------- 28 */ 29 #ifndef _LAN91C96_H_ 30 #define _LAN91C96_H_ 31 32 #include <asm/types.h> 33 #include <asm/io.h> 34 #include <config.h> 35 36 /* I want some simple types */ 37 38 typedef unsigned char byte; 39 typedef unsigned short word; 40 typedef unsigned long int dword; 41 42 /* 43 * DEBUGGING LEVELS 44 * 45 * 0 for normal operation 46 * 1 for slightly more details 47 * >2 for various levels of increasingly useless information 48 * 2 for interrupt tracking, status flags 49 * 3 for packet info 50 * 4 for complete packet dumps 51 */ 52 /*#define SMC_DEBUG 0 */ 53 54 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 55 56 #define SMC_IO_EXTENT 16 57 58 #ifdef CONFIG_CPU_PXA25X 59 60 #define SMC_IO_SHIFT 0 61 62 #define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT)) 63 64 #define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r))) 65 #define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r))) 66 #define SMC_inb(edev, p) ({ \ 67 unsigned int __p = p; \ 68 unsigned int __v = SMC_inw(edev, __p & ~1); \ 69 if (__p & 1) __v >>= 8; \ 70 else __v &= 0xff; \ 71 __v; }) 72 73 #define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) 74 #define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) 75 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 76 word __w = SMC_inw(edev, (r)&~1); \ 77 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 78 __w |= ((r)&1) ? __d<<8 : __d; \ 79 SMC_outw(edev, __w, (r)&~1); \ 80 }) 81 82 #define SMC_outsl(edev, r, b, l) ({ int __i; \ 83 dword *__b2; \ 84 __b2 = (dword *) b; \ 85 for (__i = 0; __i < l; __i++) { \ 86 SMC_outl(edev, *(__b2 + __i),\ 87 r); \ 88 } \ 89 }) 90 91 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 92 word *__b2; \ 93 __b2 = (word *) b; \ 94 for (__i = 0; __i < l; __i++) { \ 95 SMC_outw(edev, *(__b2 + __i),\ 96 r); \ 97 } \ 98 }) 99 100 #define SMC_insl(edev, r, b, l) ({ int __i ; \ 101 dword *__b2; \ 102 __b2 = (dword *) b; \ 103 for (__i = 0; __i < l; __i++) { \ 104 *(__b2 + __i) = SMC_inl(edev,\ 105 r); \ 106 SMC_inl(edev, 0); \ 107 }; \ 108 }) 109 110 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 111 word *__b2; \ 112 __b2 = (word *) b; \ 113 for (__i = 0; __i < l; __i++) { \ 114 *(__b2 + __i) = SMC_inw(edev,\ 115 r); \ 116 SMC_inw(edev, 0); \ 117 }; \ 118 }) 119 120 #define SMC_insb(edev, r, b, l) ({ int __i ; \ 121 byte *__b2; \ 122 __b2 = (byte *) b; \ 123 for (__i = 0; __i < l; __i++) { \ 124 *(__b2 + __i) = SMC_inb(edev,\ 125 r); \ 126 SMC_inb(edev, 0); \ 127 }; \ 128 }) 129 130 #else /* if not CONFIG_CPU_PXA25X */ 131 132 /* 133 * We have only 16 Bit PCMCIA access on Socket 0 134 */ 135 136 #define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) 137 #define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ 138 SMC_inw(edev, r)&0xFF) 139 140 #define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) 141 #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ 142 word __w = SMC_inw(edev, (r)&~1); \ 143 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 144 __w |= ((r)&1) ? __d<<8 : __d; \ 145 SMC_outw(edev, __w, (r)&~1); \ 146 }) 147 #define SMC_outsw(edev, r, b, l) ({ int __i; \ 148 word *__b2; \ 149 __b2 = (word *) b; \ 150 for (__i = 0; __i < l; __i++) { \ 151 SMC_outw(edev, *(__b2 + __i),\ 152 r); \ 153 } \ 154 }) 155 156 #define SMC_insw(edev, r, b, l) ({ int __i ; \ 157 word *__b2; \ 158 __b2 = (word *) b; \ 159 for (__i = 0; __i < l; __i++) { \ 160 *(__b2 + __i) = SMC_inw(edev,\ 161 r); \ 162 SMC_inw(edev, 0); \ 163 }; \ 164 }) 165 166 #endif 167 168 /* 169 **************************************************************************** 170 * Bank Select Field 171 **************************************************************************** 172 */ 173 #define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ 174 #define LAN91C96_BANKSELECT (0x3UC << 0) 175 #define BANK0 0x00 176 #define BANK1 0x01 177 #define BANK2 0x02 178 #define BANK3 0x03 179 #define BANK4 0x04 180 181 /* 182 **************************************************************************** 183 * EEPROM Addresses. 184 **************************************************************************** 185 */ 186 #define EEPROM_MAC_OFFSET_1 0x6020 187 #define EEPROM_MAC_OFFSET_2 0x6021 188 #define EEPROM_MAC_OFFSET_3 0x6022 189 190 /* 191 **************************************************************************** 192 * Bank 0 Register Map in I/O Space 193 **************************************************************************** 194 */ 195 #define LAN91C96_TCR 0 /* Transmit Control Register */ 196 #define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ 197 #define LAN91C96_RCR 4 /* Receive Control Register */ 198 #define LAN91C96_COUNTER 6 /* Counter Register */ 199 #define LAN91C96_MIR 8 /* Memory Information Register */ 200 #define LAN91C96_MCR 10 /* Memory Configuration Register */ 201 202 /* 203 **************************************************************************** 204 * Transmit Control Register - Bank 0 - Offset 0 205 **************************************************************************** 206 */ 207 #define LAN91C96_TCR_TXENA (0x1U << 0) 208 #define LAN91C96_TCR_LOOP (0x1U << 1) 209 #define LAN91C96_TCR_FORCOL (0x1U << 2) 210 #define LAN91C96_TCR_TXP_EN (0x1U << 3) 211 #define LAN91C96_TCR_PAD_EN (0x1U << 7) 212 #define LAN91C96_TCR_NOCRC (0x1U << 8) 213 #define LAN91C96_TCR_MON_CSN (0x1U << 10) 214 #define LAN91C96_TCR_FDUPLX (0x1U << 11) 215 #define LAN91C96_TCR_STP_SQET (0x1U << 12) 216 #define LAN91C96_TCR_EPH_LOOP (0x1U << 13) 217 #define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) 218 #define LAN91C96_TCR_FDSE (0x1U << 15) 219 220 /* 221 **************************************************************************** 222 * EPH Status Register - Bank 0 - Offset 2 223 **************************************************************************** 224 */ 225 #define LAN91C96_EPHSR_TX_SUC (0x1U << 0) 226 #define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) 227 #define LAN91C96_EPHSR_MUL_COL (0x1U << 2) 228 #define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) 229 #define LAN91C96_EPHSR_16COL (0x1U << 4) 230 #define LAN91C96_EPHSR_SQET (0x1U << 5) 231 #define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) 232 #define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) 233 #define LAN91C96_EPHSR_WAKEUP (0x1U << 8) 234 #define LAN91C96_EPHSR_LATCOL (0x1U << 9) 235 #define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) 236 #define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) 237 #define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) 238 239 #define LAN91C96_EPHSR_LINK_OK (0x1U << 14) 240 #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) 241 242 #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ 243 LAN91C96_EPHSR_MUL_COL | \ 244 LAN91C96_EPHSR_16COL | \ 245 LAN91C96_EPHSR_SQET | \ 246 LAN91C96_EPHSR_TX_DEFR | \ 247 LAN91C96_EPHSR_LATCOL | \ 248 LAN91C96_EPHSR_LOST_CARR | \ 249 LAN91C96_EPHSR_EXC_DEF | \ 250 LAN91C96_EPHSR_LINK_OK | \ 251 LAN91C96_EPHSR_TX_UNRN) 252 253 /* 254 **************************************************************************** 255 * Receive Control Register - Bank 0 - Offset 4 256 **************************************************************************** 257 */ 258 #define LAN91C96_RCR_RX_ABORT (0x1U << 0) 259 #define LAN91C96_RCR_PRMS (0x1U << 1) 260 #define LAN91C96_RCR_ALMUL (0x1U << 2) 261 #define LAN91C96_RCR_RXEN (0x1U << 8) 262 #define LAN91C96_RCR_STRIP_CRC (0x1U << 9) 263 #define LAN91C96_RCR_FILT_CAR (0x1U << 14) 264 #define LAN91C96_RCR_SOFT_RST (0x1U << 15) 265 266 /* 267 **************************************************************************** 268 * Counter Register - Bank 0 - Offset 6 269 **************************************************************************** 270 */ 271 #define LAN91C96_ECR_SNGL_COL (0xFU << 0) 272 #define LAN91C96_ECR_MULT_COL (0xFU << 5) 273 #define LAN91C96_ECR_DEF_TX (0xFU << 8) 274 #define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) 275 276 /* 277 **************************************************************************** 278 * Memory Information Register - Bank 0 - OFfset 8 279 **************************************************************************** 280 */ 281 #define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ 282 283 /* 284 **************************************************************************** 285 * Memory Configuration Register - Bank 0 - Offset 10 286 **************************************************************************** 287 */ 288 #define LAN91C96_MCR_MEM_RES (0xFFU << 0) 289 #define LAN91C96_MCR_MEM_MULT (0x3U << 9) 290 #define LAN91C96_MCR_HIGH_ID (0x3U << 12) 291 292 #define LAN91C96_MCR_TRANSMIT_PAGES 0x6 293 294 /* 295 **************************************************************************** 296 * Bank 1 Register Map in I/O Space 297 **************************************************************************** 298 */ 299 #define LAN91C96_CONFIG 0 /* Configuration Register */ 300 #define LAN91C96_BASE 2 /* Base Address Register */ 301 #define LAN91C96_IA0 4 /* Individual Address Register - 0 */ 302 #define LAN91C96_IA1 5 /* Individual Address Register - 1 */ 303 #define LAN91C96_IA2 6 /* Individual Address Register - 2 */ 304 #define LAN91C96_IA3 7 /* Individual Address Register - 3 */ 305 #define LAN91C96_IA4 8 /* Individual Address Register - 4 */ 306 #define LAN91C96_IA5 9 /* Individual Address Register - 5 */ 307 #define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ 308 #define LAN91C96_CONTROL 12 /* Control Register */ 309 310 /* 311 **************************************************************************** 312 * Configuration Register - Bank 1 - Offset 0 313 **************************************************************************** 314 */ 315 #define LAN91C96_CR_INT_SEL0 (0x1U << 1) 316 #define LAN91C96_CR_INT_SEL1 (0x1U << 2) 317 #define LAN91C96_CR_RES (0x3U << 3) 318 #define LAN91C96_CR_DIS_LINK (0x1U << 6) 319 #define LAN91C96_CR_16BIT (0x1U << 7) 320 #define LAN91C96_CR_AUI_SELECT (0x1U << 8) 321 #define LAN91C96_CR_SET_SQLCH (0x1U << 9) 322 #define LAN91C96_CR_FULL_STEP (0x1U << 10) 323 #define LAN91C96_CR_NO_WAIT (0x1U << 12) 324 325 /* 326 **************************************************************************** 327 * Base Address Register - Bank 1 - Offset 2 328 **************************************************************************** 329 */ 330 #define LAN91C96_BAR_RA_BITS (0x27U << 0) 331 #define LAN91C96_BAR_ROM_SIZE (0x1U << 6) 332 #define LAN91C96_BAR_A_BITS (0xFFU << 8) 333 334 /* 335 **************************************************************************** 336 * Control Register - Bank 1 - Offset 12 337 **************************************************************************** 338 */ 339 #define LAN91C96_CTR_STORE (0x1U << 0) 340 #define LAN91C96_CTR_RELOAD (0x1U << 1) 341 #define LAN91C96_CTR_EEPROM (0x1U << 2) 342 #define LAN91C96_CTR_TE_ENABLE (0x1U << 5) 343 #define LAN91C96_CTR_CR_ENABLE (0x1U << 6) 344 #define LAN91C96_CTR_LE_ENABLE (0x1U << 7) 345 #define LAN91C96_CTR_BIT_8 (0x1U << 8) 346 #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) 347 #define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) 348 #define LAN91C96_CTR_PWRDN (0x1U << 13) 349 #define LAN91C96_CTR_RCV_BAD (0x1U << 14) 350 351 /* 352 **************************************************************************** 353 * Bank 2 Register Map in I/O Space 354 **************************************************************************** 355 */ 356 #define LAN91C96_MMU 0 /* MMU Command Register */ 357 #define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ 358 #define LAN91C96_PNR 2 /* Packet Number Register */ 359 #define LAN91C96_ARR 3 /* Allocation Result Register */ 360 #define LAN91C96_FIFO 4 /* FIFO Ports Register */ 361 #define LAN91C96_POINTER 6 /* Pointer Register */ 362 #define LAN91C96_DATA_HIGH 8 /* Data High Register */ 363 #define LAN91C96_DATA_LOW 10 /* Data Low Register */ 364 #define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ 365 #define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ 366 #define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ 367 368 /* 369 **************************************************************************** 370 * MMU Command Register - Bank 2 - Offset 0 371 **************************************************************************** 372 */ 373 #define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) 374 #define LAN91C96_MMUCR_N1 (0x1U << 1) 375 #define LAN91C96_MMUCR_N2 (0x1U << 2) 376 #define LAN91C96_MMUCR_COMMAND (0xFU << 4) 377 #define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ 378 #define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ 379 #define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ 380 #define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ 381 #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ 382 #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ 383 #define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ 384 #define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ 385 386 /* 387 **************************************************************************** 388 * Auto Tx Start Register - Bank 2 - Offset 1 389 **************************************************************************** 390 */ 391 #define LAN91C96_AUTOTX (0xFFU << 0) 392 393 /* 394 **************************************************************************** 395 * Packet Number Register - Bank 2 - Offset 2 396 **************************************************************************** 397 */ 398 #define LAN91C96_PNR_TX (0x1FU << 0) 399 400 /* 401 **************************************************************************** 402 * Allocation Result Register - Bank 2 - Offset 3 403 **************************************************************************** 404 */ 405 #define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) 406 #define LAN91C96_ARR_FAILED (0x1U << 7) 407 408 /* 409 **************************************************************************** 410 * FIFO Ports Register - Bank 2 - Offset 4 411 **************************************************************************** 412 */ 413 #define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) 414 #define LAN91C96_FIFO_TEMPTY (0x1U << 7) 415 #define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) 416 #define LAN91C96_FIFO_RXEMPTY (0x1U << 15) 417 418 /* 419 **************************************************************************** 420 * Pointer Register - Bank 2 - Offset 6 421 **************************************************************************** 422 */ 423 #define LAN91C96_PTR_LOW (0xFFU << 0) 424 #define LAN91C96_PTR_HIGH (0x7U << 8) 425 #define LAN91C96_PTR_AUTO_TX (0x1U << 11) 426 #define LAN91C96_PTR_ETEN (0x1U << 12) 427 #define LAN91C96_PTR_READ (0x1U << 13) 428 #define LAN91C96_PTR_AUTO_INCR (0x1U << 14) 429 #define LAN91C96_PTR_RCV (0x1U << 15) 430 431 #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ 432 LAN91C96_PTR_AUTO_INCR | \ 433 LAN91C96_PTR_READ) 434 435 /* 436 **************************************************************************** 437 * Data Register - Bank 2 - Offset 8 438 **************************************************************************** 439 */ 440 #define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ 441 #define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ 442 443 /* 444 **************************************************************************** 445 * Interrupt Status Register - Bank 2 - Offset 12 446 **************************************************************************** 447 */ 448 #define LAN91C96_IST_RCV_INT (0x1U << 0) 449 #define LAN91C96_IST_TX_INT (0x1U << 1) 450 #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) 451 #define LAN91C96_IST_ALLOC_INT (0x1U << 3) 452 #define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) 453 #define LAN91C96_IST_EPH_INT (0x1U << 5) 454 #define LAN91C96_IST_ERCV_INT (0x1U << 6) 455 #define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) 456 457 /* 458 **************************************************************************** 459 * Interrupt Acknowledge Register - Bank 2 - Offset 12 460 **************************************************************************** 461 */ 462 #define LAN91C96_ACK_TX_INT (0x1U << 1) 463 #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) 464 #define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) 465 #define LAN91C96_ACK_ERCV_INT (0x1U << 6) 466 467 /* 468 **************************************************************************** 469 * Interrupt Mask Register - Bank 2 - Offset 13 470 **************************************************************************** 471 */ 472 #define LAN91C96_MSK_RCV_INT (0x1U << 0) 473 #define LAN91C96_MSK_TX_INT (0x1U << 1) 474 #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) 475 #define LAN91C96_MSK_ALLOC_INT (0x1U << 3) 476 #define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) 477 #define LAN91C96_MSK_EPH_INT (0x1U << 5) 478 #define LAN91C96_MSK_ERCV_INT (0x1U << 6) 479 #define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) 480 481 /* 482 **************************************************************************** 483 * Bank 3 Register Map in I/O Space 484 ************************************************************************** 485 */ 486 #define LAN91C96_MGMT_MDO (0x1U << 0) 487 #define LAN91C96_MGMT_MDI (0x1U << 1) 488 #define LAN91C96_MGMT_MCLK (0x1U << 2) 489 #define LAN91C96_MGMT_MDOE (0x1U << 3) 490 #define LAN91C96_MGMT_LOW_ID (0x3U << 4) 491 #define LAN91C96_MGMT_IOS0 (0x1U << 8) 492 #define LAN91C96_MGMT_IOS1 (0x1U << 9) 493 #define LAN91C96_MGMT_IOS2 (0x1U << 10) 494 #define LAN91C96_MGMT_nXNDEC (0x1U << 11) 495 #define LAN91C96_MGMT_HIGH_ID (0x3U << 12) 496 497 /* 498 **************************************************************************** 499 * Revision Register - Bank 3 - Offset 10 500 **************************************************************************** 501 */ 502 #define LAN91C96_REV_REVID (0xFU << 0) 503 #define LAN91C96_REV_CHIPID (0xFU << 4) 504 505 /* 506 **************************************************************************** 507 * Early RCV Register - Bank 3 - Offset 12 508 **************************************************************************** 509 */ 510 #define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) 511 #define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) 512 513 /* 514 **************************************************************************** 515 * PCMCIA Configuration Registers 516 **************************************************************************** 517 */ 518 #define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ 519 #define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ 520 521 /* 522 **************************************************************************** 523 * PCMCIA Ethernet Configuration Option Register (ECOR) 524 **************************************************************************** 525 */ 526 #define LAN91C96_ECOR_ENABLE (0x1U << 0) 527 #define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) 528 #define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) 529 #define LAN91C96_ECOR_SRESET (0x1U << 7) 530 531 /* 532 **************************************************************************** 533 * PCMCIA Ethernet Configuration and Status Register (ECSR) 534 **************************************************************************** 535 */ 536 #define LAN91C96_ECSR_INTR (0x1U << 1) 537 #define LAN91C96_ECSR_PWRDWN (0x1U << 2) 538 #define LAN91C96_ECSR_IOIS8 (0x1U << 5) 539 540 /* 541 **************************************************************************** 542 * Receive Frame Status Word - See page 38 of the LAN91C96 specification. 543 **************************************************************************** 544 */ 545 #define LAN91C96_TOO_SHORT (0x1U << 10) 546 #define LAN91C96_TOO_LONG (0x1U << 11) 547 #define LAN91C96_ODD_FRM (0x1U << 12) 548 #define LAN91C96_BAD_CRC (0x1U << 13) 549 #define LAN91C96_BROD_CAST (0x1U << 14) 550 #define LAN91C96_ALGN_ERR (0x1U << 15) 551 552 #define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) 553 554 /* 555 **************************************************************************** 556 * Default MAC Address 557 **************************************************************************** 558 */ 559 #define MAC_DEF_HI 0x0800 560 #define MAC_DEF_MED 0x3333 561 #define MAC_DEF_LO 0x0100 562 563 /* 564 **************************************************************************** 565 * Default I/O Signature - 0x33 566 **************************************************************************** 567 */ 568 #define LAN91C96_LOW_SIGNATURE (0x33U << 0) 569 #define LAN91C96_HIGH_SIGNATURE (0x33U << 8) 570 #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) 571 572 #define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ 573 #define ETHERNET_MAX_LENGTH 1514 574 575 576 /*------------------------------------------------------------------------- 577 * I define some macros to make it easier to do somewhat common 578 * or slightly complicated, repeated tasks. 579 *------------------------------------------------------------------------- 580 */ 581 582 /* select a register bank, 0 to 3 */ 583 584 #define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } 585 586 /* this enables an interrupt in the interrupt mask register */ 587 #define SMC_ENABLE_INT(edev, x) {\ 588 unsigned char mask;\ 589 SMC_SELECT_BANK(edev, 2);\ 590 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 591 mask |= (x);\ 592 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 593 } 594 595 /* this disables an interrupt from the interrupt mask register */ 596 597 #define SMC_DISABLE_INT(edev, x) {\ 598 unsigned char mask;\ 599 SMC_SELECT_BANK(edev, 2);\ 600 mask = SMC_inb(edev, LAN91C96_INT_MASK);\ 601 mask &= ~(x);\ 602 SMC_outb(edev, mask, LAN91C96_INT_MASK); \ 603 } 604 605 /*---------------------------------------------------------------------- 606 * Define the interrupts that I want to receive from the card 607 * 608 * I want: 609 * LAN91C96_IST_EPH_INT, for nasty errors 610 * LAN91C96_IST_RCV_INT, for happy received packets 611 * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver 612 *------------------------------------------------------------------------- 613 */ 614 #define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) 615 616 #endif /* _LAN91C96_H_ */ 617
