1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _SYS_ENV_LIB_H 7 #define _SYS_ENV_LIB_H 8 9 #include "../../../drivers/ddr/marvell/a38x/ddr3_init.h" 10 11 /* Serdes definitions */ 12 #define COMMON_PHY_BASE_ADDR 0x18300 13 14 #define DEVICE_CONFIGURATION_REG0 0x18284 15 #define DEVICE_CONFIGURATION_REG1 0x18288 16 #define COMMON_PHY_CONFIGURATION1_REG 0x18300 17 #define COMMON_PHY_CONFIGURATION2_REG 0x18304 18 #define COMMON_PHY_CONFIGURATION4_REG 0x1830c 19 #define COMMON_PHY_STATUS1_REG 0x18318 20 #define COMMON_PHYS_SELECTORS_REG 0x183fc 21 #define SOC_CONTROL_REG1 0x18204 22 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0 23 #define GBE_CONFIGURATION_REG 0x18460 24 #define DEVICE_SAMPLE_AT_RESET1_REG 0x18600 25 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 26 #define DEV_ID_REG 0x18238 27 28 #define CORE_PLL_PARAMETERS_REG 0xe42e0 29 #define CORE_PLL_CONFIG_REG 0xe42e4 30 31 #define QSGMII_CONTROL_REG1 0x18494 32 33 #define DEV_ID_REG_DEVICE_ID_OFFS 16 34 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000 35 36 #define SAR_DEV_ID_OFFS 27 37 #define SAR_DEV_ID_MASK 0x7 38 39 #define POWER_AND_PLL_CTRL_REG 0xa0004 40 #define CALIBRATION_CTRL_REG 0xa0008 41 #define DFE_REG0 0xa001c 42 #define DFE_REG3 0xa0028 43 #define RESET_DFE_REG 0xa0148 44 #define LOOPBACK_REG 0xa008c 45 #define SYNC_PATTERN_REG 0xa0090 46 #define INTERFACE_REG 0xa0094 47 #define ISOLATE_REG 0xa0098 48 #define MISC_REG 0xa013c 49 #define GLUE_REG 0xa0140 50 #define GENERATION_DIVIDER_FORCE_REG 0xa0144 51 #define PCIE_REG0 0xa0120 52 #define LANE_ALIGN_REG0 0xa0124 53 #define SQUELCH_FFE_SETTING_REG 0xa0018 54 #define G1_SETTINGS_0_REG 0xa0034 55 #define G1_SETTINGS_1_REG 0xa0038 56 #define G1_SETTINGS_3_REG 0xa0440 57 #define G1_SETTINGS_4_REG 0xa0444 58 #define G2_SETTINGS_0_REG 0xa003c 59 #define G2_SETTINGS_1_REG 0xa0040 60 #define G2_SETTINGS_2_REG 0xa00f8 61 #define G2_SETTINGS_3_REG 0xa0448 62 #define G2_SETTINGS_4_REG 0xa044c 63 #define G3_SETTINGS_0_REG 0xa0044 64 #define G3_SETTINGS_1_REG 0xa0048 65 #define G3_SETTINGS_3_REG 0xa0450 66 #define G3_SETTINGS_4_REG 0xa0454 67 #define VTHIMPCAL_CTRL_REG 0xa0104 68 #define REF_REG0 0xa0134 69 #define CAL_REG6 0xa0168 70 #define RX_REG2 0xa0184 71 #define RX_REG3 0xa0188 72 #define PCIE_REG1 0xa0288 73 #define PCIE_REG3 0xa0290 74 #define LANE_CFG0_REG 0xa0600 75 #define LANE_CFG1_REG 0xa0604 76 #define LANE_CFG4_REG 0xa0620 77 #define LANE_CFG5_REG 0xa0624 78 #define GLOBAL_CLK_CTRL 0xa0704 79 #define GLOBAL_MISC_CTRL 0xa0718 80 #define GLOBAL_CLK_SRC_HI 0xa0710 81 82 #define GLOBAL_CLK_CTRL 0xa0704 83 #define GLOBAL_MISC_CTRL 0xa0718 84 #define GLOBAL_PM_CTRL 0xa0740 85 86 /* SATA registers */ 87 #define SATA_CTRL_REG_IND_ADDR 0xa80a0 88 #define SATA_CTRL_REG_IND_DATA 0xa80a4 89 90 #define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178 91 #define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8 92 #define SATA_VENDOR_PORT_0_REG_DATA 0xa817c 93 #define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc 94 95 /* Reference clock values and mask */ 96 #define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0 97 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1 98 #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2 99 #define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3 100 #define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7 101 #define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc 102 #define LANE_CFG4_REG_25MHZ_VAL 0x200 103 #define LANE_CFG4_REG_40MHZ_VAL 0x300 104 105 #define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f)) 106 #define GLOBAL_PM_CTRL_REG_MASK (~(0xff)) 107 #define LANE_CFG4_REG_MASK (~(0x1f00)) 108 109 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 110 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 111 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 112 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 113 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) 114 115 #define MAX_SELECTOR_VAL 10 116 117 /* TWSI addresses */ 118 /* starting from A38x A0, i2c address of EEPROM is 0x57 */ 119 #ifdef CONFIG_ARMADA_39X 120 #define EEPROM_I2C_ADDR 0x50 121 #else 122 #define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \ 123 MV_88F68XX_Z1_ID ? 0x50 : 0x57) 124 #endif 125 #define RD_GET_MODE_ADDR 0x4c 126 #define DB_GET_MODE_SLM1363_ADDR 0x25 127 #define DB_GET_MODE_SLM1364_ADDR 0x24 128 #define DB381_GET_MODE_SLM1426_1427_ADDR 0x56 129 130 /* DB-BP Board 'SatR' mapping */ 131 #define SATR_DB_LANE1_MAX_OPTIONS 7 132 #define SATR_DB_LANE1_CFG_MASK 0x7 133 #define SATR_DB_LANE1_CFG_OFFSET 0 134 #define SATR_DB_LANE2_MAX_OPTIONS 4 135 #define SATR_DB_LANE2_CFG_MASK 0x38 136 #define SATR_DB_LANE2_CFG_OFFSET 3 137 138 /* GP Board 'SatR' mapping */ 139 #define SATR_GP_LANE1_CFG_MASK 0x4 140 #define SATR_GP_LANE1_CFG_OFFSET 2 141 #define SATR_GP_LANE2_CFG_MASK 0x8 142 #define SATR_GP_LANE2_CFG_OFFSET 3 143 144 /* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */ 145 #define MPP_CTRL_REG 0x18000 146 #define MPP_SET_MASK (~(0xffff)) 147 #define MPP_SET_DATA (0x1111) 148 #define MPP_UART1_SET_MASK (~(0xff000)) 149 #define MPP_UART1_SET_DATA (0x66000) 150 151 #define AVS_DEBUG_CNTR_REG 0xe4124 152 #define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073 153 154 #define AVS_ENABLED_CONTROL 0xe4130 155 #define AVS_LOW_VDD_LIMIT_OFFS 4 156 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) 157 #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) 158 159 #define AVS_HIGH_VDD_LIMIT_OFFS 12 160 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) 161 #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) 162 163 /* Board ID numbers */ 164 #define MARVELL_BOARD_ID_MASK 0x10 165 /* Customer boards for A38x */ 166 #define A38X_CUSTOMER_BOARD_ID_BASE 0x0 167 #define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0) 168 #define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1) 169 #define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2) 170 #define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \ 171 A38X_CUSTOMER_BOARD_ID_BASE) 172 173 /* Marvell boards for A38x */ 174 #define A38X_MARVELL_BOARD_ID_BASE 0x10 175 #define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0) 176 #define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1) 177 #define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2) 178 #define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3) 179 #define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4) 180 #define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5) 181 #define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6) 182 #define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7) 183 #define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \ 184 A38X_MARVELL_BOARD_ID_BASE) 185 186 /* Customer boards for A39x */ 187 #define A39X_CUSTOMER_BOARD_ID_BASE 0x20 188 #define A39X_CUSTOMER_BOARD_ID0 (A39X_CUSTOMER_BOARD_ID_BASE + 0) 189 #define A39X_CUSTOMER_BOARD_ID1 (A39X_CUSTOMER_BOARD_ID_BASE + 1) 190 #define A39X_MV_MAX_CUSTOMER_BOARD_ID (A39X_CUSTOMER_BOARD_ID_BASE + 2) 191 #define A39X_MV_CUSTOMER_BOARD_NUM (A39X_MV_MAX_CUSTOMER_BOARD_ID - \ 192 A39X_CUSTOMER_BOARD_ID_BASE) 193 194 /* Marvell boards for A39x */ 195 #define A39X_MARVELL_BOARD_ID_BASE 0x30 196 #define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0) 197 #define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1) 198 #define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2) 199 #define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \ 200 A39X_MARVELL_BOARD_ID_BASE) 201 202 #ifdef CONFIG_ARMADA_38X 203 #define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE 204 #define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0 205 #define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1 206 #define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID 207 #define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM 208 #define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE 209 #define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID 210 #define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM 211 #define MV_DEFAULT_BOARD_ID DB_68XX_ID 212 #define MV_DEFAULT_DEVICE_ID MV_6811 213 #elif defined(CONFIG_ARMADA_39X) 214 #define CUTOMER_BOARD_ID_BASE A39X_CUSTOMER_BOARD_ID_BASE 215 #define CUSTOMER_BOARD_ID0 A39X_CUSTOMER_BOARD_ID0 216 #define CUSTOMER_BOARD_ID1 A39X_CUSTOMER_BOARD_ID1 217 #define MV_MAX_CUSTOMER_BOARD_ID A39X_MV_MAX_CUSTOMER_BOARD_ID 218 #define MV_CUSTOMER_BOARD_NUM A39X_MV_CUSTOMER_BOARD_NUM 219 #define MARVELL_BOARD_ID_BASE A39X_MARVELL_BOARD_ID_BASE 220 #define MV_MAX_MARVELL_BOARD_ID A39X_MV_MAX_MARVELL_BOARD_ID 221 #define MV_MARVELL_BOARD_NUM A39X_MV_MARVELL_BOARD_NUM 222 #define MV_DEFAULT_BOARD_ID A39X_DB_69XX_ID 223 #define MV_DEFAULT_DEVICE_ID MV_6920 224 #endif 225 226 #define MV_INVALID_BOARD_ID 0xffffffff 227 228 /* device revesion */ 229 #define DEV_VERSION_ID_REG 0x1823c 230 #define REVISON_ID_OFFS 8 231 #define REVISON_ID_MASK 0xf00 232 233 /* A38x revisions */ 234 #define MV_88F68XX_Z1_ID 0x0 235 #define MV_88F68XX_A0_ID 0x4 236 /* A39x revisions */ 237 #define MV_88F69XX_Z1_ID 0x2 238 239 #define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) 240 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) 241 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) 242 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) 243 #define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40)) 244 245 #define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8) 246 #define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \ 247 (MPP_REG_NUM(GPIO_NUM) * 8))); 248 #define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32) 249 #define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32) 250 251 /* device ID */ 252 /* Armada 38x Family */ 253 #define MV_6810_DEV_ID 0x6810 254 #define MV_6811_DEV_ID 0x6811 255 #define MV_6820_DEV_ID 0x6820 256 #define MV_6828_DEV_ID 0x6828 257 /* Armada 39x Family */ 258 #define MV_6920_DEV_ID 0x6920 259 #define MV_6928_DEV_ID 0x6928 260 261 enum { 262 MV_6810, 263 MV_6820, 264 MV_6811, 265 MV_6828, 266 MV_NONE, 267 MV_6920, 268 MV_6928, 269 MV_MAX_DEV_ID, 270 }; 271 272 #define MV_6820_INDEX 0 273 #define MV_6810_INDEX 1 274 #define MV_6811_INDEX 2 275 #define MV_6828_INDEX 3 276 277 #define MV_6920_INDEX 0 278 #define MV_6928_INDEX 1 279 280 #ifdef CONFIG_ARMADA_38X 281 #define MAX_DEV_ID_NUM 4 282 #else 283 #define MAX_DEV_ID_NUM 2 284 #endif 285 286 #define MV_6820_INDEX 0 287 #define MV_6810_INDEX 1 288 #define MV_6811_INDEX 2 289 #define MV_6828_INDEX 3 290 #define MV_6920_INDEX 0 291 #define MV_6928_INDEX 1 292 293 enum unit_id { 294 PEX_UNIT_ID, 295 ETH_GIG_UNIT_ID, 296 USB3H_UNIT_ID, 297 USB3D_UNIT_ID, 298 SATA_UNIT_ID, 299 QSGMII_UNIT_ID, 300 XAUI_UNIT_ID, 301 RXAUI_UNIT_ID, 302 MAX_UNITS_ID 303 }; 304 305 struct board_wakeup_gpio { 306 u32 board_id; 307 int gpio_num; 308 }; 309 310 enum suspend_wakeup_status { 311 SUSPEND_WAKEUP_DISABLED, 312 SUSPEND_WAKEUP_ENABLED, 313 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED, 314 }; 315 316 /* 317 * GPIO status indication for Suspend Wakeup: 318 * If suspend to RAM is supported and GPIO inidcation is implemented, 319 * set the gpio number 320 * If suspend to RAM is supported but GPIO indication is not implemented 321 * set '-2' 322 * If suspend to RAM is not supported set '-1' 323 */ 324 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT 325 #ifdef CONFIG_ARMADA_38X 326 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 327 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 328 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 329 }; 330 #else 331 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 332 {A39X_CUSTOMER_BOARD_ID0, -1 }, \ 333 {A39X_CUSTOMER_BOARD_ID0, -1 }, \ 334 }; 335 #endif /* CONFIG_ARMADA_38X */ 336 337 #else 338 339 #ifdef CONFIG_ARMADA_38X 340 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 341 {RD_NAS_68XX_ID, -2 }, \ 342 {DB_68XX_ID, -1 }, \ 343 {RD_AP_68XX_ID, -2 }, \ 344 {DB_AP_68XX_ID, -2 }, \ 345 {DB_GP_68XX_ID, -2 }, \ 346 {DB_BP_6821_ID, -2 }, \ 347 {DB_AMC_6820_ID, -2 }, \ 348 }; 349 #else 350 #define MV_BOARD_WAKEUP_GPIO_INFO { \ 351 {A39X_RD_69XX_ID, -1 }, \ 352 {A39X_DB_69XX_ID, -1 }, \ 353 }; 354 #endif /* CONFIG_ARMADA_38X */ 355 #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ 356 357 u32 mv_board_tclk_get(void); 358 u32 mv_board_id_get(void); 359 u32 mv_board_id_index_get(u32 board_id); 360 u32 sys_env_unit_max_num_get(enum unit_id unit); 361 enum suspend_wakeup_status sys_env_suspend_wakeup_check(void); 362 u8 sys_env_device_rev_get(void); 363 u32 sys_env_device_id_get(void); 364 u16 sys_env_model_get(void); 365 struct dlb_config *sys_env_dlb_config_ptr_get(void); 366 u32 sys_env_get_cs_ena_from_reg(void); 367 368 #endif /* _SYS_ENV_LIB_H */ 369
