1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010-2015 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 #include <asm/types.h> 7 8 /* Stabilization delays, in usec */ 9 #define PLL_STABILIZATION_DELAY (300) 10 #define IO_STABILIZATION_DELAY (1000) 11 12 #define PLLX_ENABLED (1 << 30) 13 #define CCLK_BURST_POLICY 0x20008888 14 #define SUPER_CCLK_DIVIDER 0x80000000 15 16 /* Calculate clock fractional divider value from ref and target frequencies */ 17 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 18 19 /* Calculate clock frequency value from reference and clock divider value */ 20 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 21 22 /* AVP/CPU ID */ 23 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 24 #define PG_UP_TAG_0 0x0 25 26 /* AP base physical address of internal SRAM */ 27 #define NV_PA_BASE_SRAM 0x40000000 28 29 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 30 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 31 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 32 33 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 34 #define FLOW_MODE_STOP 2 35 #define HALT_COP_EVENT_JTAG (1 << 28) 36 #define HALT_COP_EVENT_IRQ_1 (1 << 11) 37 #define HALT_COP_EVENT_FIQ_1 (1 << 9) 38 39 /* This is the main entry into U-Boot, used by the Cortex-A9 */ 40 extern void _start(void); 41 42 /** 43 * Works out the SOC/SKU type used for clocks settings 44 * 45 * @return SOC type - see TEGRA_SOC... 46 */ 47 int tegra_get_chip_sku(void); 48 49 /** 50 * Returns the pure SOC (chip ID) from the HIDREV register 51 * 52 * @return SOC ID - see CHIPID_TEGRAxx... 53 */ 54 int tegra_get_chip(void); 55 56 /** 57 * Returns the SKU ID from the sku_info register 58 * 59 * @return SKU ID - see SKU_ID_Txx... 60 */ 61 int tegra_get_sku_info(void); 62 63 /* Do any chip-specific cache config */ 64 void config_cache(void); 65 66 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 67 bool tegra_cpu_is_non_secure(void); 68 #endif 69
