/external/llvm/lib/Target/BPF/InstPrinter/ |
BPFInstPrinter.cpp | 69 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); 71 if (OffsetOp.isImm()) 72 O << formatDec(OffsetOp.getImm());
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/InstPrinter/ |
AVRInstPrinter.cpp | 150 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); 156 if (OffsetOp.isImm()) { 157 int64_t Offset = OffsetOp.getImm(); 163 } else if (OffsetOp.isExpr()) { 164 O << *OffsetOp.getExpr();
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/InstPrinter/ |
BPFInstPrinter.cpp | 68 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); 75 if (OffsetOp.isImm()) { 76 auto Imm = OffsetOp.getImm();
|
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyRegisterInfo.cpp | 112 unsigned OffsetOp = MRI.createVirtualRegister(PtrRC); 114 OffsetOp) 120 .addReg(OffsetOp);
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
WebAssemblyRegisterInfo.cpp | 118 unsigned OffsetOp = MRI.createVirtualRegister(PtrRC); 120 OffsetOp) 126 .addReg(OffsetOp);
|
/external/llvm/lib/Target/Lanai/InstPrinter/ |
LanaiInstPrinter.cpp | 224 const MCOperand &OffsetOp, 226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); 227 if (OffsetOp.isImm()) { 228 assert(isInt<SizeInBits>(OffsetOp.getImm()) && "Constant value truncated"); 229 OS << OffsetOp.getImm(); 231 OffsetOp.getExpr()->print(OS, &MAI); 238 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); 243 printMemoryImmediateOffset<16>(MAI, OffsetOp, OS); 253 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/MCTargetDesc/ |
AVRMCCodeEmitter.cpp | 138 auto OffsetOp = MI.getOperand(OpNo + 1); 157 if (OffsetOp.isImm()) { 158 OffsetBits = OffsetOp.getImm(); 159 } else if (OffsetOp.isExpr()) { 161 Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(),
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/InstPrinter/ |
LanaiInstPrinter.cpp | 224 const MCOperand &OffsetOp, 226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); 227 if (OffsetOp.isImm()) { 228 assert(isInt<SizeInBits>(OffsetOp.getImm()) && "Constant value truncated"); 229 OS << OffsetOp.getImm(); 231 OffsetOp.getExpr()->print(OS, &MAI); 238 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); 243 printMemoryImmediateOffset<16>(MAI, OffsetOp, OS); 253 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1) [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIRegisterInfo.cpp | 329 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); 330 int64_t NewOffset = OffsetOp->getImm() + Offset; 334 OffsetOp->setImm(NewOffset); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonOptAddrMode.cpp | 143 const MachineOperand &OffsetOp = MI->getOperand(3); 144 if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonOptAddrMode.cpp | 162 const MachineOperand &OffsetOp = MI.getOperand(3); 163 if (!OffsetOp.isImm() || OffsetOp.getImm() > 3) 369 MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2) 371 if (!OffsetOp.isImm()) 374 int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm(); 420 MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2) 425 OffsetOp.setImm(ImmOp.getImm() + OffsetOp.getImm());
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64FrameLowering.cpp | [all...] |
AArch64ISelDAGToDAG.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIRegisterInfo.cpp | 364 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); 365 int64_t NewOffset = OffsetOp->getImm() + Offset; 369 OffsetOp->setImm(NewOffset); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelDAGToDAG.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |