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    Searched defs:Op5 (Results 1 - 6 of 6) sorted by null

  /external/capstone/arch/XCore/
XCoreDisassembler.c 626 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
632 S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
640 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
667 unsigned Op1, Op2, Op3, Op4, Op5;
673 S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
681 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
  /external/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
682 unsigned Op1, Op2, Op3, Op4, Op5;
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
682 unsigned Op1, Op2, Op3, Op4, Op5;
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMISelLowering.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]

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