1 /* 2 * Copyright 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef BRW_PIPE_CONTROL_DOT_H 25 #define BRW_PIPE_CONTROL_DOT_H 26 27 struct brw_context; 28 struct gen_device_info; 29 struct brw_bo; 30 31 /** @{ 32 * 33 * PIPE_CONTROL operation, a combination MI_FLUSH and register write with 34 * additional flushing control. 35 */ 36 #define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) 37 #define PIPE_CONTROL_CS_STALL (1 << 20) 38 #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19) 39 #define PIPE_CONTROL_TLB_INVALIDATE (1 << 18) 40 #define PIPE_CONTROL_SYNC_GFDT (1 << 17) 41 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16) 42 #define PIPE_CONTROL_NO_WRITE (0 << 14) 43 #define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14) 44 #define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14) 45 #define PIPE_CONTROL_WRITE_TIMESTAMP (3 << 14) 46 #define PIPE_CONTROL_DEPTH_STALL (1 << 13) 47 #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12) 48 #define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11) 49 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1 << 10) /* GM45+ only */ 50 #define PIPE_CONTROL_ISP_DIS (1 << 9) 51 #define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8) 52 #define PIPE_CONTROL_FLUSH_ENABLE (1 << 7) /* Gen7+ only */ 53 /* GT */ 54 #define PIPE_CONTROL_DATA_CACHE_FLUSH (1 << 5) 55 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4) 56 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3) 57 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) 58 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) 59 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) 60 #define PIPE_CONTROL_PPGTT_WRITE (0 << 2) 61 #define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2) 62 63 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ 64 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \ 65 PIPE_CONTROL_RENDER_TARGET_FLUSH) 66 67 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ 68 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \ 69 PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ 70 PIPE_CONTROL_INSTRUCTION_INVALIDATE) 71 72 /** @} */ 73 74 int brw_init_pipe_control(struct brw_context *brw, 75 const struct gen_device_info *info); 76 void brw_fini_pipe_control(struct brw_context *brw); 77 78 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); 79 void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, 80 struct brw_bo *bo, uint32_t offset, 81 uint64_t imm); 82 void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags); 83 void brw_emit_mi_flush(struct brw_context *brw); 84 void brw_emit_post_sync_nonzero_flush(struct brw_context *brw); 85 void brw_emit_depth_stall_flushes(struct brw_context *brw); 86 void gen7_emit_vs_workaround_flush(struct brw_context *brw); 87 void gen7_emit_cs_stall_flush(struct brw_context *brw); 88 void gen10_emit_isp_disable(struct brw_context *brw); 89 90 #endif 91
