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      1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 /// \file
     10 /// This file declares the targeting of the RegisterBankInfo class for AArch64.
     11 /// \todo This should be generated by TableGen.
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
     15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
     16 
     17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
     18 
     19 #define GET_REGBANK_DECLARATIONS
     20 #include "AArch64GenRegisterBank.inc"
     21 
     22 namespace llvm {
     23 
     24 class TargetRegisterInfo;
     25 
     26 class AArch64GenRegisterBankInfo : public RegisterBankInfo {
     27 protected:
     28   enum PartialMappingIdx {
     29     PMI_None = -1,
     30     PMI_FPR16 = 1,
     31     PMI_FPR32,
     32     PMI_FPR64,
     33     PMI_FPR128,
     34     PMI_FPR256,
     35     PMI_FPR512,
     36     PMI_GPR32,
     37     PMI_GPR64,
     38     PMI_FirstGPR = PMI_GPR32,
     39     PMI_LastGPR = PMI_GPR64,
     40     PMI_FirstFPR = PMI_FPR16,
     41     PMI_LastFPR = PMI_FPR512,
     42     PMI_Min = PMI_FirstFPR,
     43   };
     44 
     45   static RegisterBankInfo::PartialMapping PartMappings[];
     46   static RegisterBankInfo::ValueMapping ValMappings[];
     47   static PartialMappingIdx BankIDToCopyMapIdx[];
     48 
     49   enum ValueMappingIdx {
     50     InvalidIdx = 0,
     51     First3OpsIdx = 1,
     52     Last3OpsIdx = 22,
     53     DistanceBetweenRegBanks = 3,
     54     FirstCrossRegCpyIdx = 25,
     55     LastCrossRegCpyIdx = 39,
     56     DistanceBetweenCrossRegCpy = 2,
     57     FPExt16To32Idx = 41,
     58     FPExt16To64Idx = 43,
     59     FPExt32To64Idx = 45,
     60     FPExt64To128Idx = 47,
     61   };
     62 
     63   static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
     64                               unsigned ValLength, const RegisterBank &RB);
     65   static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
     66                                 unsigned Size, unsigned Offset);
     67   static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
     68                                      PartialMappingIdx LastAlias,
     69                                      ArrayRef<PartialMappingIdx> Order);
     70 
     71   static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
     72 
     73   /// Get the pointer to the ValueMapping representing the RegisterBank
     74   /// at \p RBIdx with a size of \p Size.
     75   ///
     76   /// The returned mapping works for instructions with the same kind of
     77   /// operands for up to 3 operands.
     78   ///
     79   /// \pre \p RBIdx != PartialMappingIdx::None
     80   static const RegisterBankInfo::ValueMapping *
     81   getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
     82 
     83   /// Get the pointer to the ValueMapping of the operands of a copy
     84   /// instruction from the \p SrcBankID register bank to the \p DstBankID
     85   /// register bank with a size of \p Size.
     86   static const RegisterBankInfo::ValueMapping *
     87   getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
     88 
     89   /// Get the instruction mapping for G_FPEXT.
     90   ///
     91   /// \pre (DstSize, SrcSize) pair is one of the following:
     92   ///      (32, 16), (64, 16), (64, 32), (128, 64)
     93   ///
     94   /// \return An InstructionMapping with statically allocated OperandsMapping.
     95   static const RegisterBankInfo::ValueMapping *
     96   getFPExtMapping(unsigned DstSize, unsigned SrcSize);
     97 
     98 #define GET_TARGET_REGBANK_CLASS
     99 #include "AArch64GenRegisterBank.inc"
    100 };
    101 
    102 /// This class provides the information for the target register banks.
    103 class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
    104   /// See RegisterBankInfo::applyMapping.
    105   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
    106 
    107   /// Get an instruction mapping where all the operands map to
    108   /// the same register bank and have similar size.
    109   ///
    110   /// \pre MI.getNumOperands() <= 3
    111   ///
    112   /// \return An InstructionMappings with a statically allocated
    113   /// OperandsMapping.
    114   const InstructionMapping &
    115   getSameKindOfOperandsMapping(const MachineInstr &MI) const;
    116 
    117 public:
    118   AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
    119 
    120   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
    121                     unsigned Size) const override;
    122 
    123   const RegisterBank &
    124   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
    125 
    126   InstructionMappings
    127   getInstrAlternativeMappings(const MachineInstr &MI) const override;
    128 
    129   const InstructionMapping &
    130   getInstrMapping(const MachineInstr &MI) const override;
    131 };
    132 } // End llvm namespace.
    133 #endif
    134