1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <tbbr_img_def.h> 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define PLATFORM_STACK_SIZE 0x1000 18 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 20 #define PLATFORM_CLUSTER_COUNT 2 21 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 22 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 23 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 24 PLATFORM_CLUSTER1_CORE_COUNT) 25 26 #define QEMU_PRIMARY_CPU 0 27 28 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 29 PLATFORM_CORE_COUNT) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 31 32 #define PLAT_MAX_RET_STATE 1 33 #define PLAT_MAX_OFF_STATE 2 34 35 /* Local power state for power domains in Run state. */ 36 #define PLAT_LOCAL_STATE_RUN 0 37 /* Local power state for retention. Valid only for CPU power domains */ 38 #define PLAT_LOCAL_STATE_RET 1 39 /* 40 * Local power state for OFF/power-down. Valid for CPU and cluster power 41 * domains. 42 */ 43 #define PLAT_LOCAL_STATE_OFF 2 44 45 /* 46 * Macros used to parse state information from State-ID if it is using the 47 * recommended encoding for State-ID. 48 */ 49 #define PLAT_LOCAL_PSTATE_WIDTH 4 50 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 51 52 /* 53 * Some data must be aligned on the biggest cache line size in the platform. 54 * This is known only to the platform as it might have a combination of 55 * integrated and external caches. 56 */ 57 #define CACHE_WRITEBACK_SHIFT 6 58 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 59 60 /* 61 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 62 * and secure DRAM. 63 */ 64 #define SEC_ROM_BASE 0x00000000 65 #define SEC_ROM_SIZE 0x00020000 66 67 #define NS_DRAM0_BASE 0x40000000 68 #define NS_DRAM0_SIZE 0x3de00000 69 70 #define SEC_SRAM_BASE 0x0e000000 71 #define SEC_SRAM_SIZE 0x00040000 72 73 #define SEC_DRAM_BASE 0x0e100000 74 #define SEC_DRAM_SIZE 0x00f00000 75 76 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 77 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 78 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 79 80 /* 81 * ARM-TF lives in SRAM, partition it here 82 */ 83 84 #define SHARED_RAM_BASE SEC_SRAM_BASE 85 #define SHARED_RAM_SIZE 0x00001000 86 87 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 88 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 89 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 90 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 91 PLAT_QEMU_HOLD_ENTRY_SIZE) 92 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 93 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 94 #define PLAT_QEMU_HOLD_STATE_WAIT 0 95 #define PLAT_QEMU_HOLD_STATE_GO 1 96 97 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 98 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 99 100 /* 101 * BL1 specific defines. 102 * 103 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 104 * addresses. 105 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 106 * the current BL1 RW debug size plus a little space for growth. 107 */ 108 #define BL1_RO_BASE SEC_ROM_BASE 109 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 110 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) 111 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 112 113 /* 114 * BL2 specific defines. 115 * 116 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 117 * size plus a little space for growth. 118 */ 119 #define BL2_BASE (BL31_BASE - 0x1D000) 120 #define BL2_LIMIT BL31_BASE 121 122 /* 123 * BL3-1 specific defines. 124 * 125 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 126 * current BL3-1 debug size plus a little space for growth. 127 */ 128 #define BL31_BASE (BL31_LIMIT - 0x20000) 129 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 130 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 131 132 133 /* 134 * BL3-2 specific defines. 135 * 136 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 137 */ 138 #define BL32_SRAM_BASE BL_RAM_BASE 139 #define BL32_SRAM_LIMIT BL31_BASE 140 #define BL32_DRAM_BASE SEC_DRAM_BASE 141 #define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) 142 143 #define SEC_SRAM_ID 0 144 #define SEC_DRAM_ID 1 145 146 #if BL32_RAM_LOCATION_ID == SEC_SRAM_ID 147 # define BL32_MEM_BASE BL_RAM_BASE 148 # define BL32_MEM_SIZE BL_RAM_SIZE 149 # define BL32_BASE BL32_SRAM_BASE 150 # define BL32_LIMIT BL32_SRAM_LIMIT 151 #elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID 152 # define BL32_MEM_BASE SEC_DRAM_BASE 153 # define BL32_MEM_SIZE SEC_DRAM_SIZE 154 # define BL32_BASE BL32_DRAM_BASE 155 # define BL32_LIMIT BL32_DRAM_LIMIT 156 #else 157 # error "Unsupported BL32_RAM_LOCATION_ID value" 158 #endif 159 160 #define NS_IMAGE_OFFSET 0x60000000 161 162 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 163 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 164 #define MAX_MMAP_REGIONS 8 165 #define MAX_XLAT_TABLES 6 166 #define MAX_IO_DEVICES 3 167 #define MAX_IO_HANDLES 4 168 169 /* 170 * PL011 related constants 171 */ 172 #define UART0_BASE 0x09000000 173 #define UART1_BASE 0x09040000 174 #define UART0_CLK_IN_HZ 1 175 #define UART1_CLK_IN_HZ 1 176 177 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 178 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 179 180 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 181 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 182 183 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 184 185 #define QEMU_FLASH0_BASE 0x04000000 186 #define QEMU_FLASH0_SIZE 0x04000000 187 188 #define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE 189 #define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE 190 191 #define DEVICE0_BASE 0x08000000 192 #define DEVICE0_SIZE 0x00021000 193 #define DEVICE1_BASE 0x09000000 194 #define DEVICE1_SIZE 0x00011000 195 196 /* 197 * GIC related constants 198 */ 199 200 #define GICD_BASE 0x8000000 201 #define GICC_BASE 0x8010000 202 #define GICR_BASE 0 203 204 205 #define QEMU_IRQ_SEC_SGI_0 8 206 #define QEMU_IRQ_SEC_SGI_1 9 207 #define QEMU_IRQ_SEC_SGI_2 10 208 #define QEMU_IRQ_SEC_SGI_3 11 209 #define QEMU_IRQ_SEC_SGI_4 12 210 #define QEMU_IRQ_SEC_SGI_5 13 211 #define QEMU_IRQ_SEC_SGI_6 14 212 #define QEMU_IRQ_SEC_SGI_7 15 213 214 /* 215 * DT related constants 216 */ 217 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 218 #define PLAT_QEMU_DT_MAX_SIZE 0x10000 219 220 /* 221 * System counter 222 */ 223 #define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) 224 225 #endif /* __PLATFORM_DEF_H__ */ 226
