1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __LS1088A_QDS_H 7 #define __LS1088A_QDS_H 8 9 #include "ls1088a_common.h" 10 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 18 #if defined(CONFIG_QSPI_BOOT) 19 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 20 #define CONFIG_ENV_SECT_SIZE 0x40000 21 #elif defined(CONFIG_SD_BOOT) 22 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 23 #define CONFIG_SYS_MMC_ENV_DEV 0 24 #define CONFIG_ENV_SIZE 0x2000 25 #else 26 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 27 #define CONFIG_ENV_SECT_SIZE 0x20000 28 #define CONFIG_ENV_SIZE 0x20000 29 #endif 30 31 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 32 #define CONFIG_QIXIS_I2C_ACCESS 33 #define SYS_NO_FLASH 34 35 #undef CONFIG_CMD_IMLS 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_DDR_CLK_FREQ 100000000 38 #else 39 #define CONFIG_QIXIS_I2C_ACCESS 40 #define CONFIG_SYS_I2C_EARLY_INIT 41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 42 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 43 #endif 44 45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 46 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 47 48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 49 50 #define CONFIG_DDR_SPD 51 #define CONFIG_DDR_ECC 52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 53 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 54 #define SPD_EEPROM_ADDRESS 0x51 55 #define CONFIG_SYS_SPD_BUS_NUM 0 56 57 58 /* 59 * IFC Definitions 60 */ 61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 62 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 64 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 65 66 #define CONFIG_SYS_NOR0_CSPR \ 67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 68 CSPR_PORT_SIZE_16 | \ 69 CSPR_MSEL_NOR | \ 70 CSPR_V) 71 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 72 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 73 CSPR_PORT_SIZE_16 | \ 74 CSPR_MSEL_NOR | \ 75 CSPR_V) 76 #define CONFIG_SYS_NOR1_CSPR \ 77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 78 CSPR_PORT_SIZE_16 | \ 79 CSPR_MSEL_NOR | \ 80 CSPR_V) 81 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 83 CSPR_PORT_SIZE_16 | \ 84 CSPR_MSEL_NOR | \ 85 CSPR_V) 86 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 88 FTIM0_NOR_TEADC(0x5) | \ 89 FTIM0_NOR_TAVDS(0x6) | \ 90 FTIM0_NOR_TEAHC(0x5)) 91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 92 FTIM1_NOR_TRAD_NOR(0x1a) | \ 93 FTIM1_NOR_TSEQRAD_NOR(0x13)) 94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 95 FTIM2_NOR_TCH(0x8) | \ 96 FTIM2_NOR_TWPH(0xe) | \ 97 FTIM2_NOR_TWP(0x1c)) 98 #define CONFIG_SYS_NOR_FTIM3 0x04000000 99 #define CONFIG_SYS_IFC_CCR 0x01000000 100 101 #ifndef SYS_NO_FLASH 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_FLASH_CFI 104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 105 #define CONFIG_SYS_FLASH_QUIET_TEST 106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 107 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 115 CONFIG_SYS_FLASH_BASE + 0x40000000} 116 #endif 117 #endif 118 119 #define CONFIG_NAND_FSL_IFC 120 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 121 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 122 123 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 126 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 127 | CSPR_V) 128 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 129 130 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 134 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 135 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 136 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 137 138 #define CONFIG_SYS_NAND_ONFI_DETECTION 139 140 /* ONFI NAND Flash mode0 Timing Params */ 141 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 142 FTIM0_NAND_TWP(0x18) | \ 143 FTIM0_NAND_TWCHT(0x07) | \ 144 FTIM0_NAND_TWH(0x0a)) 145 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 146 FTIM1_NAND_TWBE(0x39) | \ 147 FTIM1_NAND_TRR(0x0e) | \ 148 FTIM1_NAND_TRP(0x18)) 149 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 150 FTIM2_NAND_TREH(0x0a) | \ 151 FTIM2_NAND_TWHRE(0x1e)) 152 #define CONFIG_SYS_NAND_FTIM3 0x0 153 154 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_MTD_NAND_VERIFY_WRITE 157 #define CONFIG_CMD_NAND 158 159 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 160 161 #define CONFIG_FSL_QIXIS 162 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 163 #define QIXIS_LBMAP_SWITCH 6 164 #define QIXIS_QMAP_MASK 0xe0 165 #define QIXIS_QMAP_SHIFT 5 166 #define QIXIS_LBMAP_MASK 0x0f 167 #define QIXIS_LBMAP_SHIFT 0 168 #define QIXIS_LBMAP_DFLTBANK 0x0e 169 #define QIXIS_LBMAP_ALTBANK 0x2e 170 #define QIXIS_LBMAP_SD 0x00 171 #define QIXIS_LBMAP_EMMC 0x00 172 #define QIXIS_LBMAP_IFC 0x00 173 #define QIXIS_LBMAP_SD_QSPI 0x0e 174 #define QIXIS_LBMAP_QSPI 0x0e 175 #define QIXIS_RCW_SRC_IFC 0x25 176 #define QIXIS_RCW_SRC_SD 0x40 177 #define QIXIS_RCW_SRC_EMMC 0x41 178 #define QIXIS_RCW_SRC_QSPI 0x62 179 #define QIXIS_RST_CTL_RESET 0x41 180 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 181 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 182 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 183 #define QIXIS_RST_FORCE_MEM 0x01 184 #define QIXIS_STAT_PRES1 0xb 185 #define QIXIS_SDID_MASK 0x07 186 #define QIXIS_ESDHC_NO_ADAPTER 0x7 187 188 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 189 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 190 | CSPR_PORT_SIZE_8 \ 191 | CSPR_MSEL_GPCM \ 192 | CSPR_V) 193 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 194 | CSPR_PORT_SIZE_8 \ 195 | CSPR_MSEL_GPCM \ 196 | CSPR_V) 197 198 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 199 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 200 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 201 #else 202 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 203 #endif 204 /* QIXIS Timing parameters*/ 205 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 206 FTIM0_GPCM_TEADC(0x0e) | \ 207 FTIM0_GPCM_TEAHC(0x0e)) 208 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 209 FTIM1_GPCM_TRAD(0x3f)) 210 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 211 FTIM2_GPCM_TCH(0xf) | \ 212 FTIM2_GPCM_TWP(0x3E)) 213 #define SYS_FPGA_CS_FTIM3 0x0 214 215 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 216 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 217 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 224 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 225 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 226 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 227 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 228 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 229 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 230 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 231 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 232 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 233 #else 234 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 235 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 236 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 237 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 238 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 239 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 240 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 241 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 242 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 243 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 244 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 245 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 246 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 247 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 248 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 249 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 250 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 251 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 252 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 253 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 254 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 255 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 256 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 257 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 258 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 259 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 260 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 261 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 262 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 263 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 264 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 265 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 266 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 267 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 268 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 269 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 270 #endif 271 272 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 273 274 /* 275 * I2C bus multiplexer 276 */ 277 #define I2C_MUX_PCA_ADDR_PRI 0x77 278 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 279 #define I2C_RETIMER_ADDR 0x18 280 #define I2C_RETIMER_ADDR2 0x19 281 #define I2C_MUX_CH_DEFAULT 0x8 282 #define I2C_MUX_CH5 0xD 283 284 #define I2C_MUX_CH_VOL_MONITOR 0xA 285 286 /* Voltage monitor on channel 2*/ 287 #define I2C_VOL_MONITOR_ADDR 0x63 288 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 289 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 290 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 291 #define I2C_SVDD_MONITOR_ADDR 0x4F 292 293 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 294 #define CONFIG_VID 295 296 /* The lowest and highest voltage allowed for LS1088AQDS */ 297 #define VDD_MV_MIN 819 298 #define VDD_MV_MAX 1212 299 300 #define CONFIG_VOL_MONITOR_LTC3882_SET 301 #define CONFIG_VOL_MONITOR_LTC3882_READ 302 303 /* PM Bus commands code for LTC3882*/ 304 #define PMBUS_CMD_PAGE 0x0 305 #define PMBUS_CMD_READ_VOUT 0x8B 306 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 307 #define PMBUS_CMD_VOUT_COMMAND 0x21 308 309 #define PWM_CHANNEL0 0x0 310 311 /* 312 * RTC configuration 313 */ 314 #define RTC 315 #define CONFIG_RTC_PCF8563 1 316 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 317 #define CONFIG_CMD_DATE 318 319 /* EEPROM */ 320 #define CONFIG_ID_EEPROM 321 #define CONFIG_SYS_I2C_EEPROM_NXID 322 #define CONFIG_SYS_EEPROM_BUS_NUM 0 323 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 324 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 327 328 /* QSPI device */ 329 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 330 #define CONFIG_FSL_QSPI 331 #define FSL_QSPI_FLASH_SIZE (1 << 26) 332 #define FSL_QSPI_FLASH_NUM 2 333 334 #endif 335 336 #ifdef CONFIG_FSL_DSPI 337 #define CONFIG_SPI_FLASH_STMICRO 338 #define CONFIG_SPI_FLASH_SST 339 #define CONFIG_SPI_FLASH_EON 340 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 341 #define CONFIG_SF_DEFAULT_BUS 1 342 #define CONFIG_SF_DEFAULT_CS 0 343 #endif 344 #endif 345 346 #define CONFIG_CMD_MEMINFO 347 #define CONFIG_SYS_MEMTEST_START 0x80000000 348 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 349 350 #ifdef CONFIG_SPL_BUILD 351 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 352 #else 353 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 354 #endif 355 356 #define CONFIG_FSL_MEMAC 357 358 /* MMC */ 359 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 360 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 361 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 362 363 /* Initial environment variables */ 364 #ifdef CONFIG_SECURE_BOOT 365 #undef CONFIG_EXTRA_ENV_SETTINGS 366 #define CONFIG_EXTRA_ENV_SETTINGS \ 367 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 368 "loadaddr=0x90100000\0" \ 369 "kernel_addr=0x100000\0" \ 370 "ramdisk_addr=0x800000\0" \ 371 "ramdisk_size=0x2000000\0" \ 372 "fdt_high=0xa0000000\0" \ 373 "initrd_high=0xffffffffffffffff\0" \ 374 "kernel_start=0x1000000\0" \ 375 "kernel_load=0xa0000000\0" \ 376 "kernel_size=0x2800000\0" \ 377 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 378 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ 379 "sf read 0xa0e00000 0xe00000 0x100000;" \ 380 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ 381 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 382 "mcmemsize=0x70000000 \0" 383 #else /* if !(CONFIG_SECURE_BOOT) */ 384 #if defined(CONFIG_QSPI_BOOT) 385 #undef CONFIG_EXTRA_ENV_SETTINGS 386 #define CONFIG_EXTRA_ENV_SETTINGS \ 387 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 388 "loadaddr=0x90100000\0" \ 389 "kernel_addr=0x100000\0" \ 390 "ramdisk_addr=0x800000\0" \ 391 "ramdisk_size=0x2000000\0" \ 392 "fdt_high=0xa0000000\0" \ 393 "initrd_high=0xffffffffffffffff\0" \ 394 "kernel_start=0x1000000\0" \ 395 "kernel_load=0xa0000000\0" \ 396 "kernel_size=0x2800000\0" \ 397 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 398 "sf read 0x80100000 0xE00000 0x100000;" \ 399 "fsl_mc start mc 0x80000000 0x80100000\0" \ 400 "mcmemsize=0x70000000 \0" 401 #elif defined(CONFIG_SD_BOOT) 402 #undef CONFIG_EXTRA_ENV_SETTINGS 403 #define CONFIG_EXTRA_ENV_SETTINGS \ 404 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 405 "loadaddr=0x90100000\0" \ 406 "kernel_addr=0x800\0" \ 407 "ramdisk_addr=0x800000\0" \ 408 "ramdisk_size=0x2000000\0" \ 409 "fdt_high=0xa0000000\0" \ 410 "initrd_high=0xffffffffffffffff\0" \ 411 "kernel_start=0x8000\0" \ 412 "kernel_load=0xa0000000\0" \ 413 "kernel_size=0x14000\0" \ 414 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 415 "mmc read 0x80100000 0x7000 0x800;" \ 416 "fsl_mc start mc 0x80000000 0x80100000\0" \ 417 "mcmemsize=0x70000000 \0" 418 #else /* NOR BOOT */ 419 #undef CONFIG_EXTRA_ENV_SETTINGS 420 #define CONFIG_EXTRA_ENV_SETTINGS \ 421 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 422 "loadaddr=0x90100000\0" \ 423 "kernel_addr=0x100000\0" \ 424 "ramdisk_addr=0x800000\0" \ 425 "ramdisk_size=0x2000000\0" \ 426 "fdt_high=0xa0000000\0" \ 427 "initrd_high=0xffffffffffffffff\0" \ 428 "kernel_start=0x1000000\0" \ 429 "kernel_load=0xa0000000\0" \ 430 "kernel_size=0x2800000\0" \ 431 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 432 "mcmemsize=0x70000000 \0" 433 #endif 434 #endif /* CONFIG_SECURE_BOOT */ 435 436 #ifdef CONFIG_FSL_MC_ENET 437 #define CONFIG_FSL_MEMAC 438 #define CONFIG_PHYLIB 439 #define CONFIG_PHYLIB_10G 440 #define CONFIG_PHY_VITESSE 441 #define CONFIG_PHY_REALTEK 442 #define CONFIG_PHY_TERANETICS 443 #define RGMII_PHY1_ADDR 0x1 444 #define RGMII_PHY2_ADDR 0x2 445 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 446 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 447 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 448 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 449 450 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 451 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 452 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 453 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 454 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 455 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 456 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 457 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 458 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 459 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 460 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 461 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 462 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 463 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 464 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 465 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 466 467 #define CONFIG_MII /* MII PHY management */ 468 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 469 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 470 471 #endif 472 473 #define BOOT_TARGET_DEVICES(func) \ 474 func(USB, usb, 0) \ 475 func(MMC, mmc, 0) \ 476 func(SCSI, scsi, 0) \ 477 func(DHCP, dhcp, na) 478 #include <config_distro_bootcmd.h> 479 480 #include <asm/fsl_secure_boot.h> 481 482 #endif /* __LS1088A_QDS_H */ 483
