1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (c) 2015 Purna Chandra Mandal <purna.mandal (at) microchip.com> 4 * 5 */ 6 7 #ifndef __CLK_MICROCHIP_PIC32 8 #define __CLK_MICROCHIP_PIC32 9 10 /* clock output indices */ 11 #define BASECLK 0 12 #define PLLCLK 1 13 #define MPLL 2 14 #define SYSCLK 3 15 #define PB1CLK 4 16 #define PB2CLK 5 17 #define PB3CLK 6 18 #define PB4CLK 7 19 #define PB5CLK 8 20 #define PB6CLK 9 21 #define PB7CLK 10 22 #define REF1CLK 11 23 #define REF2CLK 12 24 #define REF3CLK 13 25 #define REF4CLK 14 26 #define REF5CLK 15 27 28 #endif /* __CLK_MICROCHIP_PIC32 */ 29
