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    Searched refs:MPLL (Results 1 - 7 of 7) sorted by null

  /external/u-boot/arch/arm/mach-s5pc1xx/include/mach/
clk.h 12 #define MPLL 1
  /external/u-boot/include/dt-bindings/clock/
microchip,clock.h 13 #define MPLL 2
  /external/u-boot/arch/arm/mach-exynos/include/mach/
clk.h 11 #define MPLL 1
  /external/u-boot/arch/arm/mach-s5pc1xx/
clock.c 36 case MPLL:
87 case MPLL:
107 if (pllreg == APLL || pllreg == MPLL)
206 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
  /external/u-boot/arch/arm/mach-exynos/
clock.c 125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
195 case MPLL:
225 case MPLL:
256 case MPLL:
277 /* According to the user manual, in EVT1 MPLL and BPLL always gives
278 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
279 if (pllreg == MPLL || pllreg == BPLL) {
283 case MPLL:
314 case MPLL:
437 sclk = exynos5_get_pll_clk(MPLL);
    [all...]
  /external/u-boot/arch/mips/mach-pic32/
cpu.c 157 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
  /external/u-boot/drivers/clk/
clk_pic32.c 356 case MPLL:

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