| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 141 unsigned SPReg = MRI.createVirtualRegister(PtrRC);
151 StackSize ? SPReg : (unsigned)WebAssembly::SP32)
164 .addReg(SPReg)
195 unsigned SPReg = 0;
206 SPReg = MRI.createVirtualRegister(PtrRC);
207 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg)
211 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32;
214 writeSPToMemory(SPReg, MF, MBB, InsertAddr, InsertPt, DL);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 128 unsigned SPReg = MI.getOperand(0).getReg();
129 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
130 emitMask(SPReg, LoadStoreStackMaskReg, STI);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 137 unsigned SPReg = MI.getOperand(0).getReg();
138 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
139 emitMask(SPReg, LoadStoreStackMaskReg, STI);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVFrameLowering.cpp | 103 unsigned SPReg = getSPReg(STI);
121 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
134 adjustReg(MBB, MBBI, DL, FPReg, SPReg,
146 unsigned SPReg = getSPReg(STI);
161 adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
167 adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
276 unsigned SPReg = RISCV::X2;
294 adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 149 unsigned SPReg = WebAssembly::SP32;
151 SPReg = MRI.createVirtualRegister(PtrRC);
155 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GET_GLOBAL_I32), SPReg)
164 .addReg(SPReg);
173 .addReg(SPReg)
216 unsigned SPReg = 0;
220 SPReg = FI->getBasePointerVreg();
230 SPReg = MRI.createVirtualRegister(PtrRC);
231 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg)
235 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86RetpolineThunks.cpp | 231 const unsigned SPReg = Is64Bit ? X86::RSP : X86::ESP;
232 addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(MovOpc)), SPReg, false, 0)
|
| X86CallLowering.cpp | 113 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
114 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
120 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
|
| X86FrameLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64CallLowering.cpp | 136 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
137 MIRBuilder.buildCopy(SPReg, AArch64::SP);
143 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMCallLowering.cpp | 101 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
102 MIRBuilder.buildCopy(SPReg, ARM::SP);
108 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsCallLowering.cpp | 156 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
157 MIRBuilder.buildCopy(SPReg, Mips::SP);
163 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.cpp | 167 unsigned SPReg = MFI->getStackPtrOffsetReg();
169 return std::make_pair(ScratchWaveOffsetReg, SPReg);
175 return std::make_pair(ScratchWaveOffsetReg, SPReg);
196 return std::make_pair(ScratchWaveOffsetReg, SPReg);
216 return std::make_pair(ScratchWaveOffsetReg, SPReg);
254 unsigned SPReg = MFI->getStackPtrOffsetReg();
255 if (SPReg != AMDGPU::SP_REG) {
256 assert(MRI.isReserved(SPReg) && "SPReg used but not reserved");
263 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::COPY), SPReg)
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 747 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
856 .addReg(SPReg);
885 .addReg(SPReg);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| IRTranslator.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 757 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
866 .addReg(SPReg);
895 .addReg(SPReg);
900 .addReg(SPReg);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
