| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 407 unsigned SrcReg2 =
412 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
455 // Clear any intervening kills of SrcReg and SrcReg2.
459 if (SrcReg2)
460 MBBI->clearRegisterKills(SrcReg2, TRI);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64SIMDInstrOpt.cpp | 439 unsigned SrcReg2 = MI.getOperand(3).getReg();
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) {
448 .addReg(SrcReg2, Src2IsKill)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 524 // SrcReg2 is the register if the source operand is a register,
528 unsigned SrcReg2 =
533 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
581 // Clear any intervening kills of SrcReg and SrcReg2.
585 if (SrcReg2)
586 MBBI->clearRegisterKills(SrcReg2, TRI);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 571 unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
575 SrcsReg2.push_back(SrcReg2);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 565 unsigned SrcReg, SrcReg2;
567 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
569 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
573 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 610 unsigned SrcReg, SrcReg2;
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
614 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 690 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
693 unsigned &SrcReg2, int &CmpMask,
712 SrcReg2 = MI.getOperand(2).getReg();
721 SrcReg2 = 0;
731 SrcReg2 = 0;
883 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
913 if (CmpValue != 0 || SrcReg2 != 0)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 876 unsigned SrcReg2 = 0;
878 SrcReg2 = getRegForValue(SrcValue2);
879 if (SrcReg2 == 0)
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
893 SrcReg2 = ExtReg;
899 .addReg(SrcReg1).addReg(SrcReg2);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
