1 //===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This pass: 11 // (1) tries to remove compares if CC already contains the required information 12 // (2) fuses compares and branches into COMPARE AND BRANCH instructions 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "SystemZ.h" 17 #include "SystemZInstrInfo.h" 18 #include "SystemZTargetMachine.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/ADT/StringRef.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/MachineInstr.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineOperand.h" 28 #include "llvm/CodeGen/TargetRegisterInfo.h" 29 #include "llvm/CodeGen/TargetSubtargetInfo.h" 30 #include "llvm/MC/MCInstrDesc.h" 31 #include <cassert> 32 #include <cstdint> 33 34 using namespace llvm; 35 36 #define DEBUG_TYPE "systemz-elim-compare" 37 38 STATISTIC(BranchOnCounts, "Number of branch-on-count instructions"); 39 STATISTIC(LoadAndTraps, "Number of load-and-trap instructions"); 40 STATISTIC(EliminatedComparisons, "Number of eliminated comparisons"); 41 STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions"); 42 43 namespace { 44 45 // Represents the references to a particular register in one or more 46 // instructions. 47 struct Reference { 48 Reference() = default; 49 50 Reference &operator|=(const Reference &Other) { 51 Def |= Other.Def; 52 Use |= Other.Use; 53 return *this; 54 } 55 56 explicit operator bool() const { return Def || Use; } 57 58 // True if the register is defined or used in some form, either directly or 59 // via a sub- or super-register. 60 bool Def = false; 61 bool Use = false; 62 }; 63 64 class SystemZElimCompare : public MachineFunctionPass { 65 public: 66 static char ID; 67 68 SystemZElimCompare(const SystemZTargetMachine &tm) 69 : MachineFunctionPass(ID) {} 70 71 StringRef getPassName() const override { 72 return "SystemZ Comparison Elimination"; 73 } 74 75 bool processBlock(MachineBasicBlock &MBB); 76 bool runOnMachineFunction(MachineFunction &F) override; 77 78 MachineFunctionProperties getRequiredProperties() const override { 79 return MachineFunctionProperties().set( 80 MachineFunctionProperties::Property::NoVRegs); 81 } 82 83 private: 84 Reference getRegReferences(MachineInstr &MI, unsigned Reg); 85 bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare, 86 SmallVectorImpl<MachineInstr *> &CCUsers); 87 bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare, 88 SmallVectorImpl<MachineInstr *> &CCUsers); 89 bool convertToLoadAndTest(MachineInstr &MI, MachineInstr &Compare, 90 SmallVectorImpl<MachineInstr *> &CCUsers); 91 bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare, 92 SmallVectorImpl<MachineInstr *> &CCUsers, 93 unsigned ConvOpc = 0); 94 bool optimizeCompareZero(MachineInstr &Compare, 95 SmallVectorImpl<MachineInstr *> &CCUsers); 96 bool fuseCompareOperations(MachineInstr &Compare, 97 SmallVectorImpl<MachineInstr *> &CCUsers); 98 99 const SystemZInstrInfo *TII = nullptr; 100 const TargetRegisterInfo *TRI = nullptr; 101 }; 102 103 char SystemZElimCompare::ID = 0; 104 105 } // end anonymous namespace 106 107 // Return true if CC is live out of MBB. 108 static bool isCCLiveOut(MachineBasicBlock &MBB) { 109 for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) 110 if ((*SI)->isLiveIn(SystemZ::CC)) 111 return true; 112 return false; 113 } 114 115 // Returns true if MI is an instruction whose output equals the value in Reg. 116 static bool preservesValueOf(MachineInstr &MI, unsigned Reg) { 117 switch (MI.getOpcode()) { 118 case SystemZ::LR: 119 case SystemZ::LGR: 120 case SystemZ::LGFR: 121 case SystemZ::LTR: 122 case SystemZ::LTGR: 123 case SystemZ::LTGFR: 124 case SystemZ::LER: 125 case SystemZ::LDR: 126 case SystemZ::LXR: 127 case SystemZ::LTEBR: 128 case SystemZ::LTDBR: 129 case SystemZ::LTXBR: 130 if (MI.getOperand(1).getReg() == Reg) 131 return true; 132 } 133 134 return false; 135 } 136 137 // Return true if any CC result of MI would (perhaps after conversion) 138 // reflect the value of Reg. 139 static bool resultTests(MachineInstr &MI, unsigned Reg) { 140 if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() && 141 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg) 142 return true; 143 144 return (preservesValueOf(MI, Reg)); 145 } 146 147 // Describe the references to Reg or any of its aliases in MI. 148 Reference SystemZElimCompare::getRegReferences(MachineInstr &MI, unsigned Reg) { 149 Reference Ref; 150 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { 151 const MachineOperand &MO = MI.getOperand(I); 152 if (MO.isReg()) { 153 if (unsigned MOReg = MO.getReg()) { 154 if (TRI->regsOverlap(MOReg, Reg)) { 155 if (MO.isUse()) 156 Ref.Use = true; 157 else if (MO.isDef()) 158 Ref.Def = true; 159 } 160 } 161 } 162 } 163 return Ref; 164 } 165 166 // Return true if this is a load and test which can be optimized the 167 // same way as compare instruction. 168 static bool isLoadAndTestAsCmp(MachineInstr &MI) { 169 // If we during isel used a load-and-test as a compare with 0, the 170 // def operand is dead. 171 return (MI.getOpcode() == SystemZ::LTEBR || 172 MI.getOpcode() == SystemZ::LTDBR || 173 MI.getOpcode() == SystemZ::LTXBR) && 174 MI.getOperand(0).isDead(); 175 } 176 177 // Return the source register of Compare, which is the unknown value 178 // being tested. 179 static unsigned getCompareSourceReg(MachineInstr &Compare) { 180 unsigned reg = 0; 181 if (Compare.isCompare()) 182 reg = Compare.getOperand(0).getReg(); 183 else if (isLoadAndTestAsCmp(Compare)) 184 reg = Compare.getOperand(1).getReg(); 185 assert(reg); 186 187 return reg; 188 } 189 190 // Compare compares the result of MI against zero. If MI is an addition 191 // of -1 and if CCUsers is a single branch on nonzero, eliminate the addition 192 // and convert the branch to a BRCT(G) or BRCTH. Return true on success. 193 bool SystemZElimCompare::convertToBRCT( 194 MachineInstr &MI, MachineInstr &Compare, 195 SmallVectorImpl<MachineInstr *> &CCUsers) { 196 // Check whether we have an addition of -1. 197 unsigned Opcode = MI.getOpcode(); 198 unsigned BRCT; 199 if (Opcode == SystemZ::AHI) 200 BRCT = SystemZ::BRCT; 201 else if (Opcode == SystemZ::AGHI) 202 BRCT = SystemZ::BRCTG; 203 else if (Opcode == SystemZ::AIH) 204 BRCT = SystemZ::BRCTH; 205 else 206 return false; 207 if (MI.getOperand(2).getImm() != -1) 208 return false; 209 210 // Check whether we have a single JLH. 211 if (CCUsers.size() != 1) 212 return false; 213 MachineInstr *Branch = CCUsers[0]; 214 if (Branch->getOpcode() != SystemZ::BRC || 215 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP || 216 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_NE) 217 return false; 218 219 // We already know that there are no references to the register between 220 // MI and Compare. Make sure that there are also no references between 221 // Compare and Branch. 222 unsigned SrcReg = getCompareSourceReg(Compare); 223 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch; 224 for (++MBBI; MBBI != MBBE; ++MBBI) 225 if (getRegReferences(*MBBI, SrcReg)) 226 return false; 227 228 // The transformation is OK. Rebuild Branch as a BRCT(G) or BRCTH. 229 MachineOperand Target(Branch->getOperand(2)); 230 while (Branch->getNumOperands()) 231 Branch->RemoveOperand(0); 232 Branch->setDesc(TII->get(BRCT)); 233 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch); 234 MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target); 235 // Add a CC def to BRCT(G), since we may have to split them again if the 236 // branch displacement overflows. BRCTH has a 32-bit displacement, so 237 // this is not necessary there. 238 if (BRCT != SystemZ::BRCTH) 239 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); 240 MI.eraseFromParent(); 241 return true; 242 } 243 244 // Compare compares the result of MI against zero. If MI is a suitable load 245 // instruction and if CCUsers is a single conditional trap on zero, eliminate 246 // the load and convert the branch to a load-and-trap. Return true on success. 247 bool SystemZElimCompare::convertToLoadAndTrap( 248 MachineInstr &MI, MachineInstr &Compare, 249 SmallVectorImpl<MachineInstr *> &CCUsers) { 250 unsigned LATOpcode = TII->getLoadAndTrap(MI.getOpcode()); 251 if (!LATOpcode) 252 return false; 253 254 // Check whether we have a single CondTrap that traps on zero. 255 if (CCUsers.size() != 1) 256 return false; 257 MachineInstr *Branch = CCUsers[0]; 258 if (Branch->getOpcode() != SystemZ::CondTrap || 259 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP || 260 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_EQ) 261 return false; 262 263 // We already know that there are no references to the register between 264 // MI and Compare. Make sure that there are also no references between 265 // Compare and Branch. 266 unsigned SrcReg = getCompareSourceReg(Compare); 267 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch; 268 for (++MBBI; MBBI != MBBE; ++MBBI) 269 if (getRegReferences(*MBBI, SrcReg)) 270 return false; 271 272 // The transformation is OK. Rebuild Branch as a load-and-trap. 273 while (Branch->getNumOperands()) 274 Branch->RemoveOperand(0); 275 Branch->setDesc(TII->get(LATOpcode)); 276 MachineInstrBuilder(*Branch->getParent()->getParent(), Branch) 277 .add(MI.getOperand(0)) 278 .add(MI.getOperand(1)) 279 .add(MI.getOperand(2)) 280 .add(MI.getOperand(3)); 281 MI.eraseFromParent(); 282 return true; 283 } 284 285 // If MI is a load instruction, try to convert it into a LOAD AND TEST. 286 // Return true on success. 287 bool SystemZElimCompare::convertToLoadAndTest( 288 MachineInstr &MI, MachineInstr &Compare, 289 SmallVectorImpl<MachineInstr *> &CCUsers) { 290 291 // Try to adjust CC masks for the LOAD AND TEST opcode that could replace MI. 292 unsigned Opcode = TII->getLoadAndTest(MI.getOpcode()); 293 if (!Opcode || !adjustCCMasksForInstr(MI, Compare, CCUsers, Opcode)) 294 return false; 295 296 // Rebuild to get the CC operand in the right place. 297 MachineInstr *BuiltMI = 298 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode)); 299 for (const auto &MO : MI.operands()) 300 BuiltMI->addOperand(MO); 301 BuiltMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 302 MI.eraseFromParent(); 303 304 return true; 305 } 306 307 // The CC users in CCUsers are testing the result of a comparison of some 308 // value X against zero and we know that any CC value produced by MI would 309 // also reflect the value of X. ConvOpc may be used to pass the transfomed 310 // opcode MI will have if this succeeds. Try to adjust CCUsers so that they 311 // test the result of MI directly, returning true on success. Leave 312 // everything unchanged on failure. 313 bool SystemZElimCompare::adjustCCMasksForInstr( 314 MachineInstr &MI, MachineInstr &Compare, 315 SmallVectorImpl<MachineInstr *> &CCUsers, 316 unsigned ConvOpc) { 317 int Opcode = (ConvOpc ? ConvOpc : MI.getOpcode()); 318 const MCInstrDesc &Desc = TII->get(Opcode); 319 unsigned MIFlags = Desc.TSFlags; 320 321 // See which compare-style condition codes are available. 322 unsigned ReusableCCMask = SystemZII::getCompareZeroCCMask(MIFlags); 323 324 // For unsigned comparisons with zero, only equality makes sense. 325 unsigned CompareFlags = Compare.getDesc().TSFlags; 326 if (CompareFlags & SystemZII::IsLogical) 327 ReusableCCMask &= SystemZ::CCMASK_CMP_EQ; 328 329 if (ReusableCCMask == 0) 330 return false; 331 332 unsigned CCValues = SystemZII::getCCValues(MIFlags); 333 assert((ReusableCCMask & ~CCValues) == 0 && "Invalid CCValues"); 334 335 bool MIEquivalentToCmp = 336 (ReusableCCMask == CCValues && 337 CCValues == SystemZII::getCCValues(CompareFlags)); 338 339 if (!MIEquivalentToCmp) { 340 // Now check whether these flags are enough for all users. 341 SmallVector<MachineOperand *, 4> AlterMasks; 342 for (unsigned int I = 0, E = CCUsers.size(); I != E; ++I) { 343 MachineInstr *MI = CCUsers[I]; 344 345 // Fail if this isn't a use of CC that we understand. 346 unsigned Flags = MI->getDesc().TSFlags; 347 unsigned FirstOpNum; 348 if (Flags & SystemZII::CCMaskFirst) 349 FirstOpNum = 0; 350 else if (Flags & SystemZII::CCMaskLast) 351 FirstOpNum = MI->getNumExplicitOperands() - 2; 352 else 353 return false; 354 355 // Check whether the instruction predicate treats all CC values 356 // outside of ReusableCCMask in the same way. In that case it 357 // doesn't matter what those CC values mean. 358 unsigned CCValid = MI->getOperand(FirstOpNum).getImm(); 359 unsigned CCMask = MI->getOperand(FirstOpNum + 1).getImm(); 360 unsigned OutValid = ~ReusableCCMask & CCValid; 361 unsigned OutMask = ~ReusableCCMask & CCMask; 362 if (OutMask != 0 && OutMask != OutValid) 363 return false; 364 365 AlterMasks.push_back(&MI->getOperand(FirstOpNum)); 366 AlterMasks.push_back(&MI->getOperand(FirstOpNum + 1)); 367 } 368 369 // All users are OK. Adjust the masks for MI. 370 for (unsigned I = 0, E = AlterMasks.size(); I != E; I += 2) { 371 AlterMasks[I]->setImm(CCValues); 372 unsigned CCMask = AlterMasks[I + 1]->getImm(); 373 if (CCMask & ~ReusableCCMask) 374 AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) | 375 (CCValues & ~ReusableCCMask)); 376 } 377 } 378 379 // CC is now live after MI. 380 if (!ConvOpc) { 381 int CCDef = MI.findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI); 382 assert(CCDef >= 0 && "Couldn't find CC set"); 383 MI.getOperand(CCDef).setIsDead(false); 384 } 385 386 // Check if MI lies before Compare. 387 bool BeforeCmp = false; 388 MachineBasicBlock::iterator MBBI = MI, MBBE = MI.getParent()->end(); 389 for (++MBBI; MBBI != MBBE; ++MBBI) 390 if (MBBI == Compare) { 391 BeforeCmp = true; 392 break; 393 } 394 395 // Clear any intervening kills of CC. 396 if (BeforeCmp) { 397 MachineBasicBlock::iterator MBBI = MI, MBBE = Compare; 398 for (++MBBI; MBBI != MBBE; ++MBBI) 399 MBBI->clearRegisterKills(SystemZ::CC, TRI); 400 } 401 402 return true; 403 } 404 405 // Return true if Compare is a comparison against zero. 406 static bool isCompareZero(MachineInstr &Compare) { 407 switch (Compare.getOpcode()) { 408 case SystemZ::LTEBRCompare: 409 case SystemZ::LTDBRCompare: 410 case SystemZ::LTXBRCompare: 411 return true; 412 413 default: 414 if (isLoadAndTestAsCmp(Compare)) 415 return true; 416 return Compare.getNumExplicitOperands() == 2 && 417 Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0; 418 } 419 } 420 421 // Try to optimize cases where comparison instruction Compare is testing 422 // a value against zero. Return true on success and if Compare should be 423 // deleted as dead. CCUsers is the list of instructions that use the CC 424 // value produced by Compare. 425 bool SystemZElimCompare::optimizeCompareZero( 426 MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) { 427 if (!isCompareZero(Compare)) 428 return false; 429 430 // Search back for CC results that are based on the first operand. 431 unsigned SrcReg = getCompareSourceReg(Compare); 432 MachineBasicBlock &MBB = *Compare.getParent(); 433 Reference CCRefs; 434 Reference SrcRefs; 435 for (MachineBasicBlock::reverse_iterator MBBI = 436 std::next(MachineBasicBlock::reverse_iterator(&Compare)), 437 MBBE = MBB.rend(); MBBI != MBBE;) { 438 MachineInstr &MI = *MBBI++; 439 if (resultTests(MI, SrcReg)) { 440 // Try to remove both MI and Compare by converting a branch to BRCT(G). 441 // or a load-and-trap instruction. We don't care in this case whether 442 // CC is modified between MI and Compare. 443 if (!CCRefs.Use && !SrcRefs) { 444 if (convertToBRCT(MI, Compare, CCUsers)) { 445 BranchOnCounts += 1; 446 return true; 447 } 448 if (convertToLoadAndTrap(MI, Compare, CCUsers)) { 449 LoadAndTraps += 1; 450 return true; 451 } 452 } 453 // Try to eliminate Compare by reusing a CC result from MI. 454 if ((!CCRefs && convertToLoadAndTest(MI, Compare, CCUsers)) || 455 (!CCRefs.Def && adjustCCMasksForInstr(MI, Compare, CCUsers))) { 456 EliminatedComparisons += 1; 457 return true; 458 } 459 } 460 SrcRefs |= getRegReferences(MI, SrcReg); 461 if (SrcRefs.Def) 462 break; 463 CCRefs |= getRegReferences(MI, SystemZ::CC); 464 if (CCRefs.Use && CCRefs.Def) 465 break; 466 } 467 468 // Also do a forward search to handle cases where an instruction after the 469 // compare can be converted, like 470 // LTEBRCompare %f0s, %f0s; %f2s = LER %f0s => LTEBRCompare %f2s, %f0s 471 for (MachineBasicBlock::iterator MBBI = 472 std::next(MachineBasicBlock::iterator(&Compare)), MBBE = MBB.end(); 473 MBBI != MBBE;) { 474 MachineInstr &MI = *MBBI++; 475 if (preservesValueOf(MI, SrcReg)) { 476 // Try to eliminate Compare by reusing a CC result from MI. 477 if (convertToLoadAndTest(MI, Compare, CCUsers)) { 478 EliminatedComparisons += 1; 479 return true; 480 } 481 } 482 if (getRegReferences(MI, SrcReg).Def) 483 return false; 484 if (getRegReferences(MI, SystemZ::CC)) 485 return false; 486 } 487 488 return false; 489 } 490 491 // Try to fuse comparison instruction Compare into a later branch. 492 // Return true on success and if Compare is therefore redundant. 493 bool SystemZElimCompare::fuseCompareOperations( 494 MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) { 495 // See whether we have a single branch with which to fuse. 496 if (CCUsers.size() != 1) 497 return false; 498 MachineInstr *Branch = CCUsers[0]; 499 SystemZII::FusedCompareType Type; 500 switch (Branch->getOpcode()) { 501 case SystemZ::BRC: 502 Type = SystemZII::CompareAndBranch; 503 break; 504 case SystemZ::CondReturn: 505 Type = SystemZII::CompareAndReturn; 506 break; 507 case SystemZ::CallBCR: 508 Type = SystemZII::CompareAndSibcall; 509 break; 510 case SystemZ::CondTrap: 511 Type = SystemZII::CompareAndTrap; 512 break; 513 default: 514 return false; 515 } 516 517 // See whether we have a comparison that can be fused. 518 unsigned FusedOpcode = 519 TII->getFusedCompare(Compare.getOpcode(), Type, &Compare); 520 if (!FusedOpcode) 521 return false; 522 523 // Make sure that the operands are available at the branch. 524 // SrcReg2 is the register if the source operand is a register, 525 // 0 if the source operand is immediate, and the base register 526 // if the source operand is memory (index is not supported). 527 unsigned SrcReg = Compare.getOperand(0).getReg(); 528 unsigned SrcReg2 = 529 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : 0; 530 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch; 531 for (++MBBI; MBBI != MBBE; ++MBBI) 532 if (MBBI->modifiesRegister(SrcReg, TRI) || 533 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) 534 return false; 535 536 // Read the branch mask, target (if applicable), regmask (if applicable). 537 MachineOperand CCMask(MBBI->getOperand(1)); 538 assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 && 539 "Invalid condition-code mask for integer comparison"); 540 // This is only valid for CompareAndBranch. 541 MachineOperand Target(MBBI->getOperand( 542 Type == SystemZII::CompareAndBranch ? 2 : 0)); 543 const uint32_t *RegMask; 544 if (Type == SystemZII::CompareAndSibcall) 545 RegMask = MBBI->getOperand(2).getRegMask(); 546 547 // Clear out all current operands. 548 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI); 549 assert(CCUse >= 0 && "BRC/BCR must use CC"); 550 Branch->RemoveOperand(CCUse); 551 // Remove target (branch) or regmask (sibcall). 552 if (Type == SystemZII::CompareAndBranch || 553 Type == SystemZII::CompareAndSibcall) 554 Branch->RemoveOperand(2); 555 Branch->RemoveOperand(1); 556 Branch->RemoveOperand(0); 557 558 // Rebuild Branch as a fused compare and branch. 559 // SrcNOps is the number of MI operands of the compare instruction 560 // that we need to copy over. 561 unsigned SrcNOps = 2; 562 if (FusedOpcode == SystemZ::CLT || FusedOpcode == SystemZ::CLGT) 563 SrcNOps = 3; 564 Branch->setDesc(TII->get(FusedOpcode)); 565 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch); 566 for (unsigned I = 0; I < SrcNOps; I++) 567 MIB.add(Compare.getOperand(I)); 568 MIB.add(CCMask); 569 570 if (Type == SystemZII::CompareAndBranch) { 571 // Only conditional branches define CC, as they may be converted back 572 // to a non-fused branch because of a long displacement. Conditional 573 // returns don't have that problem. 574 MIB.add(Target).addReg(SystemZ::CC, 575 RegState::ImplicitDefine | RegState::Dead); 576 } 577 578 if (Type == SystemZII::CompareAndSibcall) 579 MIB.addRegMask(RegMask); 580 581 // Clear any intervening kills of SrcReg and SrcReg2. 582 MBBI = Compare; 583 for (++MBBI; MBBI != MBBE; ++MBBI) { 584 MBBI->clearRegisterKills(SrcReg, TRI); 585 if (SrcReg2) 586 MBBI->clearRegisterKills(SrcReg2, TRI); 587 } 588 FusedComparisons += 1; 589 return true; 590 } 591 592 // Process all comparison instructions in MBB. Return true if something 593 // changed. 594 bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) { 595 bool Changed = false; 596 597 // Walk backwards through the block looking for comparisons, recording 598 // all CC users as we go. The subroutines can delete Compare and 599 // instructions before it. 600 bool CompleteCCUsers = !isCCLiveOut(MBB); 601 SmallVector<MachineInstr *, 4> CCUsers; 602 MachineBasicBlock::iterator MBBI = MBB.end(); 603 while (MBBI != MBB.begin()) { 604 MachineInstr &MI = *--MBBI; 605 if (CompleteCCUsers && (MI.isCompare() || isLoadAndTestAsCmp(MI)) && 606 (optimizeCompareZero(MI, CCUsers) || 607 fuseCompareOperations(MI, CCUsers))) { 608 ++MBBI; 609 MI.eraseFromParent(); 610 Changed = true; 611 CCUsers.clear(); 612 continue; 613 } 614 615 if (MI.definesRegister(SystemZ::CC)) { 616 CCUsers.clear(); 617 CompleteCCUsers = true; 618 } 619 if (MI.readsRegister(SystemZ::CC) && CompleteCCUsers) 620 CCUsers.push_back(&MI); 621 } 622 return Changed; 623 } 624 625 bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) { 626 if (skipFunction(F.getFunction())) 627 return false; 628 629 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo()); 630 TRI = &TII->getRegisterInfo(); 631 632 bool Changed = false; 633 for (auto &MBB : F) 634 Changed |= processBlock(MBB); 635 636 return Changed; 637 } 638 639 FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) { 640 return new SystemZElimCompare(TM); 641 } 642