/external/llvm/lib/Target/Lanai/ |
LanaiInstrInfo.h | 92 // SrcReg2 if having two register operands, and the value it compares against 95 unsigned &SrcReg2, int &CmpMask, 102 unsigned SrcReg2, int CmpMask, int CmpValue,
|
LanaiInstrInfo.cpp | 180 unsigned &SrcReg2, int &CmpMask, 188 SrcReg2 = 0; 194 SrcReg2 = MI.getOperand(1).getReg(); 208 unsigned SrcReg2, int ImmValue, 213 OI->getOperand(2).getReg() == SrcReg2) || 214 (OI->getOperand(1).getReg() == SrcReg2 && 286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, 306 if (SrcReg2 != 0) 332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 384 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 & [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiInstrInfo.h | 94 // SrcReg2 if having two register operands, and the value it compares against 97 unsigned &SrcReg2, int &CmpMask, 104 unsigned SrcReg2, int CmpMask, int CmpValue,
|
LanaiInstrInfo.cpp | 179 unsigned &SrcReg2, int &CmpMask, 187 SrcReg2 = 0; 193 SrcReg2 = MI.getOperand(1).getReg(); 207 unsigned SrcReg2, int ImmValue, 212 OI->getOperand(2).getReg() == SrcReg2) || 213 (OI->getOperand(1).getReg() == SrcReg2 && 285 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, 305 if (SrcReg2 != 0) 331 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 383 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 & [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZElimCompare.cpp | 407 unsigned SrcReg2 = 412 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) 455 // Clear any intervening kills of SrcReg and SrcReg2. 459 if (SrcReg2) 460 MBBI->clearRegisterKills(SrcReg2, TRI);
|
SystemZInstrInfo.h | 172 unsigned &SrcReg2, int &Mask, int &Value) const override; 174 unsigned SrcReg2, int Mask, int Value,
|
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.h | 163 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 166 unsigned &SrcReg2, int &CmpMask, 171 unsigned SrcReg2, int CmpMask, int CmpValue,
|
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.h | 250 unsigned &SrcReg2, int &Mask, int &Value) const override; 253 unsigned SrcReg2, int Mask, int Value,
|
PPCFastISel.cpp | 876 unsigned SrcReg2 = 0; 878 SrcReg2 = getRegForValue(SrcValue2); 879 if (SrcReg2 == 0) 891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) 893 SrcReg2 = ExtReg; 899 .addReg(SrcReg1).addReg(SrcReg2); [all...] |
PPCInstrInfo.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
SystemZInstrInfo.h | 210 unsigned &SrcReg2, int &Mask, int &Value) const override; 212 unsigned SrcReg2, int Mask, int Value,
|
SystemZElimCompare.cpp | 524 // SrcReg2 is the register if the source operand is a register, 528 unsigned SrcReg2 = 533 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) 581 // Clear any intervening kills of SrcReg and SrcReg2. 585 if (SrcReg2) 586 MBBI->clearRegisterKills(SrcReg2, TRI);
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.h | 193 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 196 unsigned &SrcReg2, int &CmpMask, 201 unsigned SrcReg2, int CmpMask, int CmpValue,
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.h | 315 unsigned &SrcReg2, int &Mask, int &Value) const override; 318 unsigned SrcReg2, int Mask, int Value,
|
PPCFastISel.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 250 /// in SrcReg and SrcReg2 if having two register operands, and the value it 254 unsigned &SrcReg2, int &CmpMask, 262 unsigned SrcReg2, int CmpMask, int CmpValue,
|
ARMFastISel.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 500 /// in SrcReg and SrcReg2 if having two register operands, and the value it 504 unsigned &SrcReg2, int &CmpMask, 511 unsigned SrcReg2, int CmpMask, int CmpValue,
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 281 /// in SrcReg and SrcReg2 if having two register operands, and the value it 285 unsigned &SrcReg2, int &CmpMask, 293 unsigned SrcReg2, int CmpMask, int CmpValue,
|
ARMFastISel.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86InstrInfo.h | 515 /// in SrcReg and SrcReg2 if having two register operands, and the value it 519 unsigned &SrcReg2, int &CmpMask, 526 unsigned SrcReg2, int CmpMask, int CmpValue,
|
/external/llvm/lib/CodeGen/ |
PeepholeOptimizer.cpp | 565 unsigned SrcReg, SrcReg2; 567 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) || 569 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) 573 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
PeepholeOptimizer.cpp | 610 unsigned SrcReg, SrcReg2; 612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || 614 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) 618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { [all...] |
/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
TargetInstrInfo.h | [all...] |